SLLS684I July   2006  – March 2016 TPD2E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on IO1 and IO2 and VCC Pins
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRY Package
6-Pin USON
Top View
TPD2E001 po_DRY_lls684.gif
N.C. – Not internally connected
DRL Package
5-Pin SOT
Top View
TPD2E001 po_DRL_slls684.gif
N.C. – Not internally connected
DRS Package
6-Pin WSON
Top View
TPD2E001 po_DRS_slls684.gif
N.C. – Not internally connected
DZD Package
4-Pin SOP
Top View
TPD2E001 po_DZD_slls684.gif

Pin Functions

PIN DESCRIPTION
NAME DRY
NO.		 DRL
NO.		 DRS
NO.		 DZD
NO.
EP — — EP — Exposed pad. Connect to GND.
GND 4 4 4 1 Ground
IOx 3, 6 3, 5 3, 6 2, 3 ESD-protected channel
N.C. 2, 5 2 2, 5 — No connection. Not internally connected.
VCC 1 1 1 4 Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor.