JAJSJF0D
March 2016 – August 2020
TPD3S716-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings—AEC Specification
6.3
ESD Ratings—IEC Specification
6.4
ESD Ratings—ISO Specification
6.5
Recommended Operating Conditions
6.6
Thermal Information
6.7
Electrical Characteristics
6.8
Timing Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
18
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
AEC-Q100 Qualified
8.3.2
Short-to-Battery and Short-to-Ground Protection on VBUS_CON
8.3.3
Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
8.3.4
ESD Protection on VBUS_CON, VD+, VD–
8.3.5
Low RON nFET VBUS Switch
8.3.6
High Speed Data Switches
8.3.7
Adjustable Hiccup Current Limit up to 2.4-A
8.3.8
Fast Over-Voltage Response Time
8.3.9
Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
8.3.10
Fault Output Signal
8.3.11
Thermal Shutdown Feature
8.3.12
16-Pin SSOP Package
8.3.13
Reverse Current Detection
8.4
Device Functional Modes
8.4.1
Normal Operation
8.4.2
Overvoltage Condition
8.4.3
Overcurrent Condition
8.4.4
Short-Circuit Condition
8.4.5
Device Logic Table
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Short-to-Battery Tolerance
9.2.2.2
Maximum Current on VBUS
9.2.2.3
Power Dissipation and Junction Temperature
9.2.2.4
USB Data Rate
9.2.3
Application Curves
10
Power Supply Recommendations
10.1
VBUS Path
10.2
VIN Pin
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
Layout Optimized for Thermal Performance
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Support Resources
12.3
Trademarks
12.4
静電気放電に関する注意事項
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DBQ|16
MSOI004H
サーマルパッド・メカニカル・データ
発注情報
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9.2.3
Application Curves
Figure 9-2
USB2.0 Eye Diagram (Board only, Through Path)
Figure 9-4
50-V, 1-µF X7R Ceramic Shorted to 18-V (Not Recommended)
Figure 9-6
TPD3S716-Q1 and 100-V, 1-µF X7R Shorted to 18 V (Powered Off)
Figure 9-8
TPD3S716-Q1 Maximum V
BUS
R
ON
vs. Junction Temperature
Figure 9-3
USB2.0 Eye Diagram (System from Typical Application Schematic)
Figure 9-5
100-V, 1-µF X7R Ceramic Shorted to 18 V
Figure 9-7
TPD3S716-Q1 I
VBUS
Temperature Derating Curve