JAJSJF0D March   2016  – August 2020 TPD3S716-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1.     18
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  AEC-Q100 Qualified
      2. 8.3.2  Short-to-Battery and Short-to-Ground Protection on VBUS_CON
      3. 8.3.3  Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
      4. 8.3.4  ESD Protection on VBUS_CON, VD+, VD–
      5. 8.3.5  Low RON nFET VBUS Switch
      6. 8.3.6  High Speed Data Switches
      7. 8.3.7  Adjustable Hiccup Current Limit up to 2.4-A
      8. 8.3.8  Fast Over-Voltage Response Time
      9. 8.3.9  Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
      10. 8.3.10 Fault Output Signal
      11. 8.3.11 Thermal Shutdown Feature
      12. 8.3.12 16-Pin SSOP Package
      13. 8.3.13 Reverse Current Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Overvoltage Condition
      3. 8.4.3 Overcurrent Condition
      4. 8.4.4 Short-Circuit Condition
      5. 8.4.5 Device Logic Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Short-to-Battery Tolerance
        2. 9.2.2.2 Maximum Current on VBUS
        3. 9.2.2.3 Power Dissipation and Junction Temperature
        4. 9.2.2.4 USB Data Rate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VBUS Path
    2. 10.2 VIN Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Layout Optimized for Thermal Performance
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Timing Characteristics

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, D+/D– = 45 Ω to GND, VD+/VD–/VBUS_CON = float (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ENABLE PIN
tON_HOSTHost mode enable on timeTime between VEN and DEN asserted low and VBUS and Data FETs turn on, CVBUS_CON = 0 µF5.7ms
tON_CLIENTClient mode enable on timeTime between DEN asserted low and Data FETs turn on. VEN remains high2.4ms
tOFF_HOSTHost mode disable timeTime between VEN and DEN deasserted high and VBUS and Data FETs turn off, CVBUS_CON = 0 µF30µs
tOFF_CLIENTClient mode disable timeTime between DEN deasserted high and Data FETs turn off. VEN remains high5µs
tHOST_TO_CLIENTHost to Client mode transition timeTime between VEN deasserted high and VBUS FET turns off. DEN remains low, CVBUS_CON = 0 µF70µs
tCLIENT_TO_HOSTClient to Host mode transition timeTime between VEN asserted low and VBUS FET turns on. DEN remains low, CVBUS_CON = 0 µF3.4ms
OVER CURRENT PROTECTION
tBLANKOvercurrent blanking timeTime from overcurrent condition until FLT assertion and VBUS FET turn off2ms
tRETRYOvercurrent retry timeTime from overcurrent FET shut off until FET turns back on100ms
tRECVOvercurrent recovery timeTime from end of tRETRY until FLT deassertion if overcurrent condition is removed8ms
OVER VOLTAGE PROTECTION
tOVP_responseOVP Response time – VBUSMeasured from OVP Condition to FET turnoff24µs
tOVP_responseOVP Response time – data switchesMeasured from OVP Condition to FET turnoff200ns
tOVP_ FLT_ASSERTOVP FLT assertion timeMeasured from an OVP Condition to FLT assertion14µs
SHORT TO GROUND PROTECTION
tSHRTShort to ground response timeTime from short condition until current falls below 120% of ISHRT, CVBUS_CON = 0 µF24µs
tSHRT_FLTZShort to ground FLT assertion timeTime from short condition until FLT is asserted, CVBUS_CON = 0 µF20µs
REVERSE SUPPLY DETECTION
tREV_SUPPLY_BLANKReverse supply blanking timeTime from reverse current condition until FLT assertion2ms