SLVSCO7C August   2014  – September 2017 TPD1E05U06-Q1 , TPD4E05U06-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q101 Qualification
      2. 7.3.2 IEC 61000-4-2 Level 4 ESD Protection
      3. 7.3.3 IEC 61000-4-4 EFT Protection
      4. 7.3.4 IEC 61000-4-5 Surge Protection
      5. 7.3.5 I/O Capacitance
      6. 7.3.6 DC Breakdown Voltage
      7. 7.3.7 Ultra-Low Leakage Current
      8. 7.3.8 Low ESD Clamping Voltage
      9. 7.3.9 Easy Flow-Through Routing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on Pin 1, 2, 4, or 5
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Electrical fast transient IEC 61000-4-4 (5/50 ns) 80 A
Peak pulse IEC 61000-4-5 Current (tp – 8/20 µs) 2.5 A
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD4E05U06-Q1(3) 40 W
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD1E05U06-Q1(3) 30 W
TA Operating temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are with respect to GND unless otherwise noted.
(3) Measured at 25°C

6.2 ESD Ratings—AEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per AEC Q100-002(2) ±8000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic Discharge IEC 61000-4-2 contact discharge - TPD4E05U06-Q1 (1) ±12000 V
IEC 61000-4-2 contact discharge - TPD1E05U06-Q1 ±12000
IEC 61000-4-2 air-gap discharge ±15000
(1) Measured at 25°C, per IEC 61000.4.2 Ed. 2.0 Section 7.2.4.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage 0 5.5 V
TA Operating free-air temperature –40 125 °C

6.5 Thermal Information

THERMAL METRIC(1) TPD1E05U06-Q1 TPD4E05U06-Q1 UNIT
DPY (X1SON) DQA (USON)
2 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 697.3 327 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 471 189.5 °C/W
RθJB Junction-to-board thermal resistance 575.9 257.7 °C/W
ψJT Junction-to-top characterization parameter 175.7 60.9 °C/W
ψJB Junction-to-board characterization parameter 575.1 257 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT – OUTPUT RESISTANCE
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VBR Break-down voltage IIO = 1 mA 6.4 8.7 V
VCLAMP Clamp voltage IPP = 1 A, TLP, from I/O to GND(1) 10 V
IPP = 5 A, TLP, from I/O to GND(1) 14
IPP = 1 A, TLP, from GND to I/O(1) 3
IPP = 5 A, TLP, from GND to I/O(1) 7.5
ILEAK Leakage current VIO = 2.5 V 1 10 nA
RDYN Dynamic resistance DPY package I/O to GND(2) 0.8 Ω
GND to I/O(2) 0.7
DQA package I/O to GND(2) 0.96
GND to I/O(2) 0.9
CAPACITANCE
CL Line capacitance VIO = 2.5 V, f = 1 MHz, I/O to GND TPD1E05U06-Q1 DPY package 0.42 pF
TPD4E05U06-Q1 DQA package 0.5
Δ CIO-TO-GND Variation of input capacitance GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Channel x pin to GND – channel y pin to GND		 0.05 0.08 pF
CCROSS Channel to channel input capacitance GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins 0.04 0.08 pF
(1) Transition line pulse with 100 ns width, 200 ps rise time.
(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 5 A and I = 10 A.

6.7 Typical Characteristics

TPD4E05U06-Q1 TPD1E05U06-Q1 C001_SLVSBO7.png
Figure 1. Current vs Voltage
Current vs Voltage DC Voltage Sweep I-V Curve
TPD4E05U06-Q1 TPD1E05U06-Q1 D006_SLVSCO7.gif
Figure 3. Current vs Voltage
Positive TLP Plot I/O to GND
TPD4E05U06-Q1 TPD1E05U06-Q1 C004_SLVSBO7.png
Figure 5. Leakage Current vs Temperature
TPD4E05U06-Q1 TPD1E05U06-Q1 D004_SLVSCO7.gif
Figure 7. Voltage vs Time –8-kV IEC Waveform
TPD4E05U06-Q1 TPD1E05U06-Q1 D002_SLVSCO7.gif
Figure 2. Current and Power vs Time
Surge Curve (tp = 8/20 µs), Pin I/O to GND
TPD4E05U06-Q1 TPD1E05U06-Q1 D005_SLVSCO7.gif
Figure 4. Current vs Voltage
Negative TLP Plot I/O to GND
TPD4E05U06-Q1 TPD1E05U06-Q1 D003_SLVSCO7.gif
Figure 6. Voltage vs Time 8-kV IEC Waveform
TPD4E05U06-Q1 TPD1E05U06-Q1 C009_SLVSBO7.png
Figure 8. Insertion Loss vs Frequency