SLVSC54B July   2013  – April 2014 TPD4E110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Signal range on Terminal 1, 2, 3, or 4
        2. 9.2.2.2 Operating Frequency
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Single Layer Routing
      2. 10.2.2 Double Layer Routing
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Applications and Implementation

9.1 Application Information

TPD4E110 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC.

9.2 Typical Application

cir_prot_slvsc54.gifFigure 10. Protecting a Pair of Super-Speed Data Lines

9.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Signal range on Pin 1, 2, 3, or 4 0V to 5.5V
Operating Frequency 3.0 GHz

9.2.2 Detailed Design Procedure

To begin the design process some parameters must be decided upon. The designer needs to know the following:

  • Signal range on all the protected lines
  • Operating frequency

9.2.2.1 Signal range on Terminal 1, 2, 3, or 4

TPD4E110 has 4 identical protection channels for signal lines. The symmetry of TPD4E110 provides flexibility when selecting which of the 4 IO channels will protect which signal lines. Any IO will support a signal range of 0V to 5.5V.

9.2.2.2 Operating Frequency

The 0.45pF capacitance of each IO channel supports data rates up to 6Gbps.

9.2.3 Application Curves

apps_eye1_slvsc54.pngFigure 11. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Single Layer Routing with Device Installed
apps_eye3_slvsc54.pngFigure 13. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Double Layer Routing with Device Installed
apps_eye2_slvsc54.pngFigure 12. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Single Layer Routing without Device Installed
apps_eye4_slvsc54.pngFigure 14. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Double Layer Routing with Device Installed