Firewire Interface
The TPD4S1394 provides robust system level ESD solution for the IEEE 1394 port, along with a live insertion detection mechanism for high-speed lines interfacing a low-voltage, ESD sensitive core chipset. This device protects and monitors up to two differential input pairs. The optimized line capacitance protects the data lines with data rates in excess of 1.6 GHz without degrading signal integrity.
The TPD4S1394 incorporates a live insertion detection circuit whose output state changes when improper voltage levels are present on the input data lines. The FWPWR_EN signal controls an external FireWire port power switch. During the live insertion event if there is a floating GND or a high level signal at the D+ or D– pins, the internal comparator detects the changes and pull the FWPWR_EN signal to a low state. When FWPWR_EN is driven low, there is an internal delay mechanism preventing it from being driven to the high state regardless of the inputs to the comparator.
Additionally, the TPD4S1394 performs ESD protection on the four inputs pins: D1+, D1–, D2+, and D2–. The TPD4S1394 conforms to the IEC61000-4-2 (Level 4) ESD protection and ±15-kV HBM ESD protection. The TPD4S1394 is characterized for operation over ambient air temperature of –40°C to 85°C.
A 0.1-µF decoupling capacitor is required at VCC.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPD4S1394 | X2SON (8) | 2.00 mm × 1.40 mm |
Changes from A Revision (March 2013) to B Revision
Changes from * Revision (November 2009) to A Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
D1+ | 8 | Input | High-speed ESD clamp input |
D1– | 7 | Input | High-speed ESD clamp input |
D2+ | 6 | Input | High-speed ESD clamp input |
D2– | 5 | Input | High-speed ESD clamp input |
FWPWR_EN | 4 | Output | Control output |
GND | 2 | Ground | Ground |
VCC | 1 | Power | Power supply |
VCLMP | 3 | Output | Comparator trip reference |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage | –0.5 | 4.6 | V |
VIO | IO voltage at D+, D–, VCLMP | 0 | 4 | V |
FWPWR_EN | Switch output | –0.5 | 4.6 | V |
TA | Operating free-air temperature | –40 | 85 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except 5, 6, 7, and 8 | ±2500 | V |
Pins 5, 6, 7, and 8 | ±15000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | All pins except 5, 6, 7, and 8 | ±1000 | |||
Pins 5, 6, 7, and 8 | ±1000 | ||||
IEC 61000-4-2 contact discharge | Pins 5, 6, 7, and 8 (interface side) | ±6000 | |||
IEC 61000-4-2 air-gap discharge | Pins 5, 6, 7, and 8 (interface side) | ±6000 |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
VCC | Supply voltage | 3 | 3.6 | V |
THERMAL METRIC(1) | TPD4S1394 | UNIT | |
---|---|---|---|
DQL (X2SON) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 167.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 82.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 82 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VDX | FWPWR_EN trip voltage (D+ and D– pins) |
High-to-low | 2.9 | 3.4 | 4 | V | |
Low-to-high | 2.7 | 3.2 | 3.8 | ||||
VCLMP | Value on pin | No connection | 2.45 | V | |||
VBR | Breakdown voltage at VCLAMP | II = 1 mA | 4.2 | V | |||
VD | Diode forward voltage for lower clamp | ID = 8 mA lower clamp diode | –0.6 | –0.8 | –0.95 | V | |
FWPWR_EN | Switch output | VCC | V | ||||
RDYN | Dynamic resistance (in and out clamp) of D+, D– | I = 1 A | 1 | Ω | |||
CIO | I/O capacitance of D+, D– | VIO = 2.5 V | 1.5 | 2 | pF | ||
ICC | Current consumption | VCC = 3.3 V, FWPWR_EN = high | 130 | 200 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tTRIP | Delay time for FWPWR_EN to go low | Loading on FWPWR_EN = 50 pF | 0.5 | 2 | 5 | µs |
tRESET | Delay time for FWPWR_EN to go high after trip | FWPWR_EN = VCC | 300 | 450 | 600 | ms |
D+, D– Pins |
D+, D– Pins |