SLVSA55B November   2009  – November 2016 TPD4S1394

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

TPD4S1394 has both high-speed ESD cells to protect the D1+, D1–, D2+, and D2– lines and live insertion detection circuit to identify improper status during insertion and to control the external power switch.

8.2 Typical Application

TPD4S1394 schem_slvsa55b.gif Figure 3. Typical Application Schematic

8.2.1 Design Requirements

For this design example, a TPD4S1394 is used to protect the FireWire connector and detect live insertion.

Table 1 shows the design parameters:

Table 1. Design Parameters

PARAMETER EXAMPLE VALUE
Power supply, VCC 3.3 V
Data line operating frequency 400 MHz (800 Mbps)

8.2.2 Detailed Design Procedure

The data transfer rate of 800 Mbps is well below the bandwidth of the data pins of TPD4S1394. So the parasitics associated with the ESD cells on these lines do not degrade the signal integrity. 3.3-V power supplies are commonly available from the board and can be used to power the live insertion detection circuit.

8.2.3 Application Curves

TPD4S1394 g_iocap_volt_lvsa55.gif
D+, D– Pins
Figure 4. I/O Capacitance vs I/O Voltage
TPD4S1394 g_insertloss_lvsa55.gif
D+, D– Pins
Figure 5. Insertion Loss (S21)