11.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.
  • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Avoid using VIAs between the connecter and an I/O protection pin on TPD4S214.
• Avoid 90º turns in traces.
  • Electric fields tend to build up on corners, increasing EMI coupling.
• Minimize impedance on the path to GND for maximum ESD dissipation.
• The capacitors on V_BUS and V_{OTG_IN} should be placed close to their respective pins on TDP4S214.

11.2 Layout Example

Figure 30. TPD4S214 Layout Example

Successful dissipation of an ESD event is largely dependent on minimizing the impedance along the designated electrical path to ground. For this reason any TVS, including TPD4S214, needs to have the lowest possible impedance to GND. The BGA footprint of this device constrains the path to ground through a VIA in the GND pad of TPD4S214. Due to the "skin effect," maximizing the surface area of the VIA minimizes the impedance of the path to GND. For this reason make both the VIA pad diameter and the VIA drill diameter as large as possible, thus maximizing the surface area of the outside of the VIA surface and the inside of the VIA surface. The GND plane should not be broken in the vicinity of the GND VIA. If possible, attaching the GND VIA to a GND plane on multiple layers minimizes the impedance. The GND VIA should be filled with a non-conductive filler (like epoxy) as opposed to a conductive filler, in order to keep the surface area of the inside of the VIA created by the drill. The GND VIA should be plated over at the SMD pad.