SLVSBP3C December 2012 – May 2015 TPD5S116
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
TPD5S116 provides IEC 61000-4-2 Level 4 Contact ESD rating to the HDMI 2.0 transmitter port, with backwards compatibility. Buffered voltage level translators (VLT) translate DDC and CEC channels bidirectionally. The system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines. The CEC line has an integrated 3.3-V rail, eliminating the need for a 3.3-V supply on board.
The TPD5S116 is placed as close as possible to the HDMI connector to provide voltage level translation, 5V_OUT current limiting and overall ESD protection for the HDMI Controller.
For this example, use Table 2 as the input parameters:
DESIGN PARAMETERS | EXAMPLE VALUE | ||
---|---|---|---|
Voltage on VCCA | 1.8 V | ||
Voltage on 5V_SYS | 5.0 V | ||
Drive EN low (disabled) | -0.5 – 0.4 V | ||
Drive EN low (enabled) | 1.0 V to 1.8 V | ||
Drive HPD_CON low (disabled) | 0 V – 0.8 V | ||
Drive HPD_CON high (enabled) | 2.0 V – 5.0 V | ||
Drive a logical "1" | SYS to CON | SCL and SDA | 1.26 V – 1.8 V |
CEC | |||
CON to SYS | SCL and SDA | 3.5 V – 5.0 V | |
CEC | 2.31 V – 3.3 V | ||
Drive a logical "0" | SYS to CON | SCL and SDA | -0.5 V – 0.11 V |
CEC | |||
CON to SYS | SCL and SDA | -0.5 V – 1.5 V | |
CEC | -0.5 V – 0.99 V |
To begin the design process the designer needs to know the 5V_SYS voltage range and the logic level, VCCA, voltage range.
The system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines.
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between 5V_SYS and GND. A 10-μF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD greater than CIN can cause 5V_CON to exceed 5V_SYS when the system supply is removed. A CIN to CLOAD ratio of 10 to 1 is recommended for minimizing 5V_SYS dip caused by inrush currents during startup.