The optimum placement is as close to the connector as possible.
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Avoid using VIAs between the connecter and an I/O protection pin on TPD5S116.
Avoid 90º turns in traces.
Electric fields tend to build up on corners, increasing EMI coupling.
Minimize impedance on the path to GND for maximum ESD dissipation.
The capacitors on 5V_CON and 5V_SYS should be placed close to their respective pins on TPD5S116.