SLLS685D July   2006  – September 2015 TPD6E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

TPD6E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC.

8.2 Typical Application

TPD6E001 TPD6E001_App_Diagram.gif Figure 3. Typical Application Schematic

8.2.1 Design Requirements

For this design example, a single TPD6E001 is used to protect all the pins of three USB2.0 connectors.

Given the USB application, the following parameters are known.

Table 1. Design Parameters

DESIGN PARAMETER VALUE
Signal range on IO1, IO2, IO3, IO4, IO5, IO6 0 V to 3.6 V
Signal voltage range on VCC 0 V to 5.25 V
Operating Frequency 240 MHz

8.2.2 Detailed Design Procedure

When placed near the USB connectors, the TPD6E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD6E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed:

  1. Place the TPD6E001 solution close to the connectors. This allows the TPD6E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board.
  2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event.
  3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD6E001 consumes 1 nA (max) leakage current. But during the ESD event, VCC and GND may see 15 A to
    30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike.
  4. Leave the unused IO pins floating. In this example of protecting three USB ports, none of the IO pins will be left unused.
  5. The VCC pin can be connected in two different ways:
    1. If the VCC pin is connected to the system power supply, the TPD6E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD bypass.
    2. If the VCC pin is not connected to the system power supply, the TPD6E001 can tolerate higher signal swing in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the VCC pin for ESD bypass.

8.2.3 Application Curve

Figure 4 is a capture of the voltage clamping waveform of TPD6E001 on IO1 during a +8kV Contact IEC61000-4-2 ESD strike.

TPD6E001 C001_SLLS685.png Figure 4. TPD6E001 +8kV Contact IEC61000-4-2 Voltage Clamping Waveform