SLLSE38B June   2010  – March 2016 TPD8E003

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 DC Breakdown Voltage
      5. 7.3.5 Low Leakage Current
      6. 7.3.6 Industrial Temperature Range
      7. 7.3.7 Space-Saving Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Required ESD Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

For proper operation of the ESD clamps, both during normal function and ESD events, the following layout and design guidelines must be followed:

  • Place the TPD8E003 solution close to the connector. This allows the TPD8E003 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board.
  • TI recommends employing two signal layers in the printed-circuit board (PCB) to route through the eight ESD clamp terminals of the TPD8E003.
  • Ensure that there is proper metallization for the GND vertical interconnect access (VIA). During an ESD event, the in-rush current flows to the system GND plane through the GND VIA. Having a low-impedance path allows the current to flow quickly to GND, effectively building a robust, system-level ESD immunity.
  • Place the VIA under the DQD pad in locations that offer maximum flexibility in board routing.
  • One common set of guidelines (not restricted to all cases):
    • Trace width: 4 mm
    • VIA diameter: 6 mm
    • DQD package pad dimensions: 8 mm × 12 mm

10.2 Layout Example

TPD8E003 appinfo1_llse38.gif Figure 7. Board Layout With the TPD8E003DQDR
TPD8E003 appinfo2_llse38.gif Figure 8. Top and Bottom Layer Board Layout With the TPD8E003DQDR