9.1.1 DAC Type

TPIC2010 has nine channels of Actuator. Each channel is assigned to the most suitable DAC engine with a different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types and sampling rate with 312kHz. All channel (except SLED and STP) have x6 gain. The DAC for STP is 8-bits resolution output with 40 kHz PWM, no Feed Back. The Gain for STP is 5x relative to P5V voltage. Table 36 shows configuration of each actuator.

9.1.2 Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT

The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) will be put into 8-bit current DAC in every 5 MHz. The lower 4 bits will be put into one bit current DAC in sequence from upper to lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25%, or 0%, will be summed in 8-bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4 bits summing to PWM output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is Figure 55.

Figure 55. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

9.1.3 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2010 recognizes four subordinate position bits (LSB) as 0. To arrange for 12bit DAC format, DSP should shift 8bit or 10 bit data to an appropriate bit position. The full scale is +/-1.0 V and driver gain is set 6. The output voltage (Vout) is given by the following equation:

Equation 1.

Equation 2.

where

• bit[11:0] is the digital input value, range 000000000000b to 111111111111b.

Figure 56. Output Voltage vs DAC Code

9.1.4 Example Timing of Target Control System

TPIC2010 is designed for that meets the requirements updating control data in 400 kHz. The example of control system parameter is Table 38. It takes 0.51 µs for transmit a 16-bit data packet to TPIC2010 with 35-MHz SCLK. Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8 MHz, the system designer must reduce the packet quantity under three. For example, Focus/Truck command is updating in every 2.5 µs (400 kHz), and it is able to send another two kind of packet in this same slot. Figure 57 shows the example of the control timing when TPIC2010 is used.

Figure 57. Example DAC Control

9.1.5 Spindle Motor Driver Part

When VSPM is set a positive DAC code then it’ll be into acceleration mode. “IS” mode operates then the start-up circuit offers the special start-up pattern sequence to the driver in start-up, and then switch to spin-up mode by detecting the rotor position by BEMF signal from the spindle motor coil.

The spin-down and brake function also be controlled by DAC value VSPM. When it’s set the brake command to VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin shown below.

Figure 58. Spindle Operating Sequence

• It is recommended to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be pull up to the appropriate supply voltage by external resistor.
• Short Brake mode is asserted after 300ms of FG signal stays L-level in deceleration.
• The FG Output is set to H-level in Sleep Mode in order to reduce sleep mode current.
• This value is the nominal number of using motor with 16-poles.
• First of all, power supply voltage of A5V/P5V must be supplied before any signals input.
• Internal circuit starts after 800 µs(TYP) since XMUTE changed to “H”. Recommended marginal delay value is 1ms for being ready.

9.1.5.1 Spindle PWM Control

The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always six times. However, the maximum output is restricted to P5V voltage. A dead band which output = 0 exists in the width of plus or minus 0x52 focusing on zero.

Figure 59. Spindle PWM Control

9.1.5.2 Auto Short Brake Function

TPIC2010 provides auto short brake function which is selecting brake mode automatically by motor speed. Auto Short Brake is the intelligent brake function that includes two modes: short brake and active brake. When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and silent during braking.

Table 39. Brake Mode

VSPM[11:0]	ROTATION SPEED (RPM)
	≈ 0 TO 2000	≈ 3000
0x000 - 0xFAE	2-phase short brake	2-phase short brake
0xFAE - 0xA00	Active brake	Active brake
0xA00 - 0x800	Active brake	3-phase short brake

This value is the nominal number of using motor with 16-poles motor.

Figure 60. Brake Mode Selections

9.1.5.3 Spindle Low Speed Mode

LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake mode is always short brake. Figure 61 shows the output duty of LS mode.

Figure 61. Spindle PWM Control (Low Speed Mode)

9.1.6 Sled Driver Part

The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus 0x33 focusing on zero.

Figure 62. Sled Output Current

• Both outputs of SLED1/2 are “H” when input code is in dead band.

9.1.6.1 End Detect Function

This device has the function of end position detection for Sled and Collimator lens. This function aim to eliminate the position switch at PUH inner and collimator lens end position. This function is enabled by ENDDET_ENA = 1 with setting object actuator (ENDDET_SLCT = 0: for Sled ENDDET_SLCT = 1: for Step). When this function is enabled, internal logic will detect the sled out zero-cross point and at that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There’re four threshold levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET bit will be cleared at the BEMF voltage exceed threshold again.

Figure 63. Timing of Sled End Detection

• For the purpose of getting correct stepping motor BEMF, we recommend to choose more than 110Hz (440pps) control frequency. However this control frequency depends on the stepping motor characteristic.
• BEMF detection level is selectable 22, 46, 86 mV.

Figure 64. Timing of Step End Detection

• Recommended control speed is around 1200 pps for getting correct BEMF level. It depends on the stepping motor characteristic. Please evaluate on your condition adequately.
• BEMF detection level is selectable 19, 39, 60 mV.

9.1.7 Load Driver Part

Load driver outputs the voltage with voltage feed back corresponding to the input DAC value. This channel has power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively to other actuator channels. Load driver is shared with the TRK driver.

Figure 65. Load Output Duty

• Output voltage is controlled by PWM
• Both LOAD+ and LOAD- are connected to PGND through the internal clamp diode respectively.

9.1.8 Focus/Track/Tilt Driver Part

9.1.8.1 Input vs Output Duty

Figure 66. FCS/TRK/TLT Output Duty

9.1.9 2-Channel Synchronous DC-DC Converter

TPIC2010 has two channels synchronous step-down DC-DC converters. Two converters operate with a 120-degree turn-on phase shift of the PMOS (high side) transistors. It prevents the high side switches of both regulators to be turned on simultaneously, and therefore smooth the input current. This feature reduces the surge current drawn from the supply.

Switching frequency is 2.5 MHz. Because the ripple current in the coil can reduce, the smaller inductor value can be selected. And the inductor with lowest DC resistance can be selected for highest efficiency. And the regulators have fast transient response.

9.1.9.4 Discontinuous Regulation Mode

The regulation mode called discontinuous regulation mode improves the conversion efficiency at a low current loading by changing regulation timing. Discontinuous mode is able to set 1 to SWx_MD_BURST (REG6D) bit. Figure 67 shows the discontinuous regulation action. The current consumption has been reduced by shortening the energizing time of driving FET. On the other hand, DC voltage ripple grows.

Figure 67. Discontinuous Regulation Mode

9.1.10 Monitor Signal on GPOUT

The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical sum

9.2.1 Design Requirements

To begin the design process, determine the following:

1. Motor configuration: The user can use all motor channels or some of them.
2. Power up devices with a 5-V supply.

9.2.2 Detailed Design Procedure

After power up on 5-V supply, the following values may be written to the following registers to enable motors.

1. Set WRITE_ENABLE = 1 on REG76 via SPI.
2. Set XSLEEP = 1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.

9.2.3 Application Curves

Figure 69. DAC Code vs Duty Cycle for TLT Outputs

Figure 70. DAC Code vs Duty Cycle for LOAD Outputs