SLIS093D March   2000  – March 2015 TPIC6C596

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial-In Interface
      2. 8.3.2 Clear Register
      3. 8.3.3 Output Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With V(VIN) < 4.5 V (Minimum V(VIN))
      2. 8.4.2 Operating With 5.5 V < V(VIN) < 6 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Cascaded Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 R1, R2, R3, R4, R5, R6, R7, R8 R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8 = (Vsupply - V (Dx)) / I (Dx) = (12 V - 2 V) / 0.02 A = 500 Ω
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Logic supply voltage(2) –0.3 7 V
VI Logic input voltage –0.3 7 V
VDS Power DMOS drain-to-source voltage(3) –0.3 33 V
Continuous source-to-drain diode anode current 250 mA
Pulsed source-to-drain diode anode current(4) 500 mA
ID Pulsed drain current, each output, all outputs on, TC = 25°C(4) 250 mA
ID Continuous drain current, each output, all outputs on, TC = 25°C(4) 100 mA
IDM Peak drain current single output, TC = 25°C(4) 250 mA
EAS Single-pulse avalanche energy (see Figure 11) 30 mJ
IAS Avalanche current(5) 200 mA
Continuous total dissipation See Thermal Information
TC Operating case temperature –40 125 °C
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Each power DMOS source is internally connected to GND.
(4) Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
(5) DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 11).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Logic supply voltage 4.5 5.5 V
VIH High-level input voltage 0.85 VCC V
VIL Low-level input voltage 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on(1)(2)(see Figure 7) 250 mA
tsu Setup time, SER IN high before SRCK↑ (see Figure 9) 15 ns
th Hold time, SER IN high after SRCK↑, (see Figure 9) 15 ns
tw Pulse duration (see Figure 9) 40 ns
TC Operating case temperature –40 125 °C
(1) Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
(2) Technique should limit TJ − TC to 10°C maximum.

6.4 Thermal Information

THERMAL METRIC(1) TPIC6C596 UNIT
PW (TSSOP) D (SOIC) N (PDIP)
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 109.7 83.7 51.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.6 45.1 38.3
RθJB Junction-to-board thermal resistance 54.8 41.2 31.4
ψJT Junction-to-top characterization parameter 5 12.1 23.6
ψJB Junction-to-board characterization parameter 54.2 40.9 31.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA 33 37 V
VSD Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V
VOH High-level output voltage, SER OUT IOH = − 20 µA, VCC = 4.5 V 4.4 4.49 V
IOH = − 4 mA, VCC = 4.5 V 4 4.2
VOL Low-level output voltage, SER OUT IOL = 20 µA, VCC = 4.5 V 0.005 0.1 V
IOL = 4 mA, VCC = 4.5 V 0.3 0.5
IIH High-level input current VCC = 5.5 V, VI = VCC 1 µA
IIL Low-level input current VCC = 5.5 V, VI = 0 –1 µA
ICC Logic supply current VCC = 5.5 V All outputs off 20 200 µA
All outputs on 150 500
ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz,
All outputs off,		 CL = 30 pF,
See Figure 9 and Figure 2		 1.2 5 mA
IN Nominal current VDS(on) = 0.5 V,
TC = 85°C 		IN = ID,
See (1)(2)(3)		 90 mA
IDSX OFF-state drain current VDS = 30 V, VCC = 5.5 V 0.1 0.2 µA
VDS = 30 V
TC = 125°C		 VCC = 5.5 V
 0.15 0.3
rDS(on) Static drain-source ON-state resistance ID = 50 mA,
VCC = 4.5 V		 See (1) and(2) and Figure 3 and Figure 4 6.5 9 Ω
ID = 50 mA,
TC = 125°C,
VCC = 4.5 V		 9.9 12
ID = 100 mA,
VCC = 4.5 V		 9.9 10
(1) Technique should limit TJ − TC to 10°C maximum.
(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
(3) Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C.

6.6 Switching Characteristics

VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from G CL = 30 pF, ID = 75 mA, See Figure 5, Figure 8 and Figure 9 80 ns
tPHL Propagation delay time, high-to-low-level output from G 50 ns
tr Rise time, drain output 100 ns
tf Fall time, drain output 80 ns
tpd Propagation delay time, SRCK↓ to SEROUT CL = 30 pF, ID = 75 mA, See Figure 9 15 ns
f(SRCK) Serial clock frequency CL = 30 pF, ID = 75 mA(3) 10 MHz
ta Reverse-recovery-current rise time IF = 100 mA, di/dt = 10 A/µs(1)(2),
See Figure 10		 100 ns
trr Reverse-recovery time 120
(1) Technique should limit TJ − TC to 10°C maximum.
(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
(3) This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.

6.7 Typical Characteristics

TPIC6C596 graph_01_slis093.gif
Figure 1. Peak Avalanche Current
vs Time Duration of Avalanche
TPIC6C596 graph_03_slis093.gif
Technique should limit TJ − TC to 10°C maximum.
Figure 3. Drain-to-Source ON-State Resistance
vs Drain Current
TPIC6C596 graph_05_slis093.gif
Technique should limit TJ − TC to 10°C maximum
Figure 5. Switching Time vs Case Temperature
TPIC6C596 graph_07_slis093.gif
Figure 7. Maximum Peak Drain Current of
Each Output vs Number of Outputs Conducting Simultaneously
TPIC6C596 graph_02_slis093.gif
Figure 2. Supply Current vs Frequency
TPIC6C596 graph_04_slis093.gif
Figure 4. Static Drain-to-Source ON-State Resistance
vs Logic Supply Voltage
TPIC6C596 graph_06_slis093.gif
Figure 6. Maximum Continuous Drain Current of
Each Output vs Number of Outputs Conducting Simultaneously