8.2.1.1 Design Requirements

8.2.1.2 Detailed Design Procedure

The TPL0102 can be used in rheostat mode with an OPA316 to create an adjustable gain non-inverting amplifier. The capacitor and resistor values were chosen based upon the Non-Inverting Amplifier Gain equation:

Equation 5.

Where Z_in is the impedance between the inverting input and GND and Z_f is the impedance of the feedback network.

In this application, the following equations are used:

Equation 6.

and

Equation 7.

Where R_f and C_f are the feedback resistor and capacitor, respectively.

A 100 Ω resistor is added in series with the TPL0102 resistance in order to stop the op amp from producing infinite gain. When the TPL0102 is at zero-scale, the resistance between terminal L and terminal W is ~0 Ω. This would normally cause infinite gain, but with the 100 Ω resistor is series, the lowest Z_in can be is 100 Ω, which at DC will create a gain of roughly 60 dB.

Equation 8.

R_f and C_f were chosen based upon characteristics of the potentiometer and op amp, respectively. The value of R_f affects the level of gain, primarily at low frequencies. Since the TPL0102 has a full-scale resistance of 100 kΩ between terminal W and terminal L, the Rf was chosen to match this full-scale resistance, which produces the minimum gain of 6 dB:

Equation 9.

As frequency increases, C_f begins to have an impact on gain. A frequency roll-off will occur due to the open-loop gain of the op amp, but in this application, the desired effect is to have C_f impact the roll off before the open loop gain of the op amp. At a gain of 40 dB, the op amp open loop gain will force the roll off to occur at 100 kHz. Therefore, in order for C_f to impact the roll off before the open loop gain, roll off due to the capacitor must occur at less than 100 kHz. In this application, 50 kHz is the desired roll off frequency, resulting in a C_f value of 33 pF.

Equation 10.

Measurements were taken with a 10 kΩ load. A 50 Ω resistor is included at the input for termination of measurement equipment.

8.2.1.3 Application Curves

As the TPL0102 moves from full-scale to zero-scale, Z_in decreases, which causes the gain of the op amp to increase from 6 dB to 56 dB. The amplifier does not reach the full 60 dB of calculated gain because the resistance in the TPL0102 did not reach 0 Ω. At zero-scale, the TPL0102 had a remaining resistance of approximately 58 Ω.

Equation 11.

The application curve clearly shows the effect of the low pass filter created by the R_f and C_f combination. Roll off begins as frequencies approach 50 kHz because of the pole created by the 33 pF capacitor. As the frequency increases beyond 50 kHz, the gain decreases by -20 dB/dec until the gain levels off at 1V/V or 0dB. The gain levels off due to the nature of non-inverting op amp transfer functions. The feedback impedance, Z_f, is approximately zero at high frequency because C_f acts as a short. As shown below, this results in a gain of 0 dB:

Equation 12.

At approximately 3 MHz, the gain is again reduced by –20 dB/dec due to the pole created by open-loop gain of the OPA316.

Figure 32. Gain vs Frequency

8.2.2.1 Design Requirements

8.2.2.2 Detailed Design Procedure

The TPL0102 can be used in voltage divider mode with a unity-gain op amp buffer to create an 8-bit Digital to Analog Converter (DAC). The analog output voltage of the circuit is determined by the wiper setting programmed through the I²C bus.

The op amp is required to buffer the high-impedance output of the TPL0102 or else loading placed on the output of the voltage divider will affect the output voltage.

8.2.2.3 Application Curves

The voltage at terminal H determines the maximum analog voltage at the output. As the TPL0102 moves from zero-scale to full-scale, the voltage divider adjusts with relation to the voltage divider formula (Equation 1), resulting in the desired voltage at terminal W. The voltage at terminal W will range linearly from 0 V to the terminal H voltage. In this example, Vin at terminal H is 5 V and 2.7 V.

Figure 34. TPL0102 Digital Input vs OPA320 Analog Output (DAC)

8.2.3.1 Design Requirements

8.2.3.2 Detailed Design Procedure

Both potentiometers within the TPL0102 can be used with an OPA317 op amp and N-Channel MOSFET to produce a variable current sink. The first potentiometer, configured in voltage divider mode, is used to set the input voltage to the OPA317. The second potentiometer, configured in rheostat mode, is used to set the span of the current (I_LOAD) running through R_LOAD. The load current for the circuit is shown below:

Equation 13.

Based upon the voltage divider formula between the setting of the TPL0102 and the 150 kΩ resistor, the voltage at the positive input of the OPA317, V_set, can range from 0 to 2 V. This leaves a maximum of 3 V of voltage drop from the positive side to the negative side of the external load with a 5 V supply. A 1.2 kΩ resistor is placed in series with the TPL0102 span setting potentiometer (R_set). At full scale of the span setting potentiometer and the maximum voltage at V_set (2 V), the maximum value for I_LOAD is:

Equation 14.

When the span setting potentiometer is at zero scale with the maximum voltage at V_set, the maximum value for I_LOAD is:

Equation 15.

The same calculations can be made when the potentiometer in voltage divider mode is a zero scale. At zero scale, V_set will be almost negligible, resulting in 0 A of current no matter the value of the span setting potentiometer.

8.2.3.3 Application Curves

As the TPL0102 in rheostat mode (span setting potentiometer) moves from zero-scale to full-scale, a new step (line) is created with a larger achievable maximum current. The rheostat mode potentiometer directly corresponds to R_set in Equation 13. The TPL0102 in voltage divider mode produces the granular current values between the minimum and maximum range. The voltage divider potentiometer directly corresponds to V_set in Equation 13. For example, when the potentiometer in rheostat mode is at code 256, the potentiometer in voltage divider mode produces a theoretical maximum current of 1.33 mA at code 256 and a minimum current of 0 µA at code 0.

The current sink does not reach the full 1.33 mA because of the error in resistance of the span setting potentiometer. At full-scale, the resistor had an actual resistance of 480 Ω.

Equation 16.

Figure 36. Current vs Span Setting Code