SNAS629C JULY   2013  – December 2014 TPL5100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements TCAL, MOS_DRV, DONE, PGOOD
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supervisor Feature
      2. 7.3.2 Calibration Pulse
        1. 7.3.2.1 Overview of the Timing Signals MOS_DRV, TCAL, and DONE
      3. 7.3.3 Configuration and Interface
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Supply Voltage (VDD-GND) -0.3 6 V
Input voltage -0.3 VDD+0.3 V
Voltage between any two pins(3) -0.3 VDD+0.3 V
Input Current on any pin -5 5 mA
Junction Temperature, TJ(4) 150 °C
Storage temperature, Tstg -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to ground unless otherwise noted.
(3) When the input voltage (VIN) at any pin exceeds the power supply (VDD), the current on that pin must not exceed 5 mA and the voltage must also not exceed 6.0 V.
(4) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Ratings

MIN MAX UNIT
Supply Voltage (VDD-GND) 1.8 5.0 V
Temperature Range -40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TPL5100 UNIT
VSSOP
10 PINS
RθJA Junction-to-ambient thermal resistance 196.8 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics(1)

Specifications are for TA =TJ = 25°C, VDD-GND=2.5 V, unless otherwise stated.
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
POWER SUPPLY
IVDD Supply current(4) PGOOD=VDD 30 50 nA
PGOOD=GND 12 nA
TIMER
tDP Timer Delay Period 16, 32, 64, 100, 128, 256, 512, 1024 s
Timer Delay Period drift over life time(5) 0.06 %
Timer Delay Period drift over temperature 400 ppm/°C
tCAL Calibration pulse width 14.063 15.625 17.188 ms
tDP to tCAL matching error(6) VDD<=3.0 V 0.1%
tDONE DONE Pulse width(6) 100 ns
tMOS_DRV MOS_DRV Pulse width 31.25 ms
DIGITAL LOGIC LEVELS
VIH Logic High Threshold PGOOD, DONE 0.7xVDD V
VIL Logic Low Threshold PGOOD, DONE 0.3xVDD V
VOH Logic output High Level MOS_DRV, TCAL

Iout = 100 uA 		VDD-0.3 V
MOS_DRV, TCAL

Iout = 1 mA 		VDD-0.7 V
VOL Logic output Low Level MOS_DRV, TCAL

Iout = -100 uA 		0.3 V
MOS_DRV, TCAL

Iout = -1 mA 		0.7 V
(1) Electrical Characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA..
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) The supply current doesn’t take in account load and pull-up resistor current. Input pins are at GND or VDD.
(5) Operational life time test procedure equivalent to 10 years.
(6) Ensured by design.

6.6 Timing Requirements TCAL, MOS_DRV, DONE, PGOOD

MIN NOM MAX UNIT
trTCAL Rise Time TCAL Capacitve load 15 pF 50 ns
tfTCAL Fall Time TCAL Capacitve load 15 pF 50 ns
trMOS_DRV Rise Time MOS_DRV Capacitve load 50 pF 4 ns
tfMOS_DRV Fall Time MOS_DRV Capacitve load 50 pF 50 ns
tDDONE DONE to MOS_DRV delay Min delay 100 ns
Max delay tDP-5 × tCAL ms
tDTCAL TCAL to MOS_DRV delay tCAL/2 ms
Timing(2).gifFigure 1. Timing Diagram

6.7 Typical Characteristics

C004_SNAS629.png
Figure 2. IDD vs Temperature
C001_SNAS629.png
Figure 4. TCAL Pulse Width vs Temperature
C003_SNAS629.png
Figure 3. IDD vs VDD
C002_SNAS629.png
Figure 5. TCAL Pulse Width vs VDD