JAJSOQ1 October   2023 TPS1210-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 9.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 9.3.3 Short-Circuit Protection
        1. 9.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 9.3.3.2 Short-Circuit Protection With Latch-Off
      4. 9.3.4 Undervoltage Protection (UVLO)
      5. 9.3.5 Reverse Polarity Protection
      6. 9.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 9.3.7 TPS1210x-Q1 as a Simple Gate Driver
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Limitations
        1. 10.1.1.1 Short-Circuit Protection Delay
        2. 10.1.1.2 Short-Circuit Protection Threshold
    2. 10.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20220531-SS0I-QNR1-0SV6-PZZ5Z6XJKTSH-low.svgFigure 6-1 VSSOP19-Pin DGX Top View
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMETPS1210x-Q1
DGX-19 (VSSOP)
EN/UVLO1I

EN/UVLO Input. A voltage on this pin above 1.21 V enables normal operation. Forcing this pin below 0.3 V shuts down the device reducing quiescent current to approximately 1.6 µA (typical). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout.

When EN/UVLO is left floating an internal pull down of 100 nA pulls EN/UVLO low and keeps the device in shutdown state.

INP2

2I

Input Signal for external charge FET control. In TPS12100-Q1 drive INP2 high to drive G2 high. Drive INP2 low to pull G2 low.

INP2 has an internal weak 100-nA pulldown to GND to keep G2 pulled low to SRC when INP2 is left floating.

In TPS12101-Q1 drive INP2 low to drive G2 high. Drive INP2 high to pull G2 low. INP2 has an internal weak pulldown of 100 nA to GND to keep G2 high when INP2 is left floating.

INP1

3

I

Input Signal for external charge FET control. In TPS12100-Q1 drive INP1 high to drive G1PU high. Drive INP1 low to pull G1PD low. INP1 has an internal weak pulldown of 100 nA to GND to keep G1PD pulled to SRC when INP1 is left floating.

In TPS12101-Q1, drive INP1 low to drive G1PU high. Drive INP1 high to pull G1PD low. INP1 has an internal weak pull down of 100 nA to GND to keep G1PU high when INP1 is left floating.

N.C

4

—No connect
FLT

5

OOpen Drain Fault Output. This pin asserts low during short-circuit fault, charge pump UVLO, input UVLO and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND.
GND6GConnect GND to system ground
CS_SEL7

I

Current sense select input. Connect this pin to ground to activate high side current sense. Drive this pin to > 2 V to activate low side current sensing.

CS_SEL has an internal weak pull down of 100 nA to GND.

ISCP8I

Short-circuit detection setting. A resistor across ISCP to GND sets the short circuit current comparator threshold.
If short-circuit protection feature is not desired then connect CS+, CS– , VS pins together and connect ISCP, TMR pins to GND.

TMR9IFault Timer Input. A capacitor across TMR pin to GND sets the delay time for short-circuit fault turn-off .
Leave this pin open for fastest response setting. If short-circuit protection feature is not desired then connect CS+, CS–, VS pins together and connect ISCP, TMR pins to GND.
SCP_TEST10I

Internal short-circuit comparator (SCP) diagnosis input.

When SCP_TEST is driven low to high with INP1 pulled high, the internal SCP comparator operation is checked. FLT goes low and G1PD gets pulled to SRC if SCP comparator is functional.

Connect SCP_TEST pin to GND if this feature is not desired.

SCP_TEST has an internal weak pulldown of 100 nA to GND.

G211O

Charging FET gate drive output. This pin has 1.69-A peak source and 2-A sink capacity. Leave the G2 pin floating if the G2 drive functionality is unused.

BST12OHigh Side Bootstrapped Supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC.
SRC13OSource connection of the external FET
G1PD14OHigh Current Gate Driver Pull-Down. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET.
G1PU15OHigh Current Gate Driver Pull-Up. This pin pulls up to BST. Connect this pin to G1PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on.
CS-17ICurrent sense negative input
CS+18ICurrent sense positive input

N.C

19—

No connect

VS20PowerSupply pin of the controller
(1) I = input, O = output, I/O = input and output, P = power, G = Ground