JAJSOQ1 October   2023 TPS1210-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 9.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 9.3.3 Short-Circuit Protection
        1. 9.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 9.3.3.2 Short-Circuit Protection With Latch-Off
      4. 9.3.4 Undervoltage Protection (UVLO)
      5. 9.3.5 Reverse Polarity Protection
      6. 9.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 9.3.7 TPS1210x-Q1 as a Simple Gate Driver
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Limitations
        1. 10.1.1.1 Short-Circuit Protection Delay
        2. 10.1.1.2 Short-Circuit Protection Threshold
    2. 10.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1.1.1 Short-Circuit Protection Delay

In application designs with high side current sense configurations as shown in Figure 9-5 and Figure 9-6 with CTMR = Open, the short-circuit protection delay during power up with output short circuited does not match the specified maximum value of 10 µs.

Testing has shown that the actual short-circuit protection delay during power up by EN/UVLO signal is approximately 70 µs. This increase in protection delay still allows for the TPS1210-Q1 to operate as designed, but results in larger power dissipation in the external MOSFET during output short-circuit scenario.

A design fix must be included in the final version of the IC.