JAJSOQ1 October   2023 TPS1210-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 9.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 9.3.3 Short-Circuit Protection
        1. 9.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 9.3.3.2 Short-Circuit Protection With Latch-Off
      4. 9.3.4 Undervoltage Protection (UVLO)
      5. 9.3.5 Reverse Polarity Protection
      6. 9.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 9.3.7 TPS1210x-Q1 as a Simple Gate Driver
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Limitations
        1. 10.1.1.1 Short-Circuit Protection Delay
        2. 10.1.1.2 Short-Circuit Protection Threshold
    2. 10.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3 Short-Circuit Protection

The TPS1210x-Q1 feature adjustable short-circuit protection. The threshold and response time can be adjusted using RSCP resistor and CTMR capacitor respectively. The device senses the voltage across CS+ and CS– pins.

These pins can be connected across an external high and low side current sense resistor (RSNS) or across the FET drain and source terminals for FET RDSON sensing as shown in Figure 9-5, Figure 9-6 and Figure 9-7 respectively.

GUID-20230423-SS0I-XDKT-NWDC-PZ31XGM4ZJ0H-low.svgFigure 9-5 TPS12100-Q1 Application Circuit With External Sense Resistor RSNS based High Side Current Sensing
GUID-20230423-SS0I-TFMH-SH6Q-SGJSTJDLWLTP-low.svgFigure 9-7 TPS12100-Q1 Application Circuit with External Sense Resistor RSNS based Low Side Current Sensing
GUID-20230423-SS0I-GMZZ-WPH3-TQTPPKJVJJCB-low.svgFigure 9-6 TPS12100-Q1 Application Circuit With MOSFET RDSON based Current Sensing

Set the short-circuit detection threshold using an external RSCP resistor across ISCP and GND pins. Use Equation 5 to calculate the required RSCP value:

Equation 5. RSCP (Ω)= ISC×RSNS - 10 mV2 μA

Refer to Equation 9 in Application Limitations section for update in equation in final revision of IC.

Where,

RSNS is the current sense resistor value or the FET RDSON value.

ISC is the desired short-circuit current level.

The short-circuit protection response is fastest with no CTMR cap connected across TMR and GND pins.

With the device powered ON and EN/UVLO, INP1 pulled high, During Q1 turn-ON, first VGS of external FET Q1 (G1 gate drive) is sensed by monitoring the voltage across G1PD to SRC. Once G1PD to SRC voltage raises above V(G1_GOOD) threshold which ensures that the external FET is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the short-circuit set point (V(SCP)), G1PD pulls low to SRC and FLT asserts low. Subsequent events can be set either to be auto-retry or latch off as described in following sections.