JAJSM93B june   2022  – may 2023 TPS1641

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Shutdown Input (EN/SHDN)
      2. 8.3.2  Overvoltage Protection (OVP)
      3. 8.3.3  Output Slew Rate and Inrush Current Control (dVdt)
      4. 8.3.4  Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
      5. 8.3.5  Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
        1. 8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
      6. 8.3.6  Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
      7. 8.3.7  Fast-Trip and Short-Circuit Protection
      8. 8.3.8  Analog Load Current Monitor (IMON) on the IOCP Pin
      9. 8.3.9  IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
      10. 8.3.10 Thermal Shutdown and Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Overvoltage Setpoints
        2. 9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
        3. 9.2.2.3 Setting the Output Power Limit
        4. 9.2.2.4 Monitoring the Output Current
        5. 9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
    4. 9.4 Best Design Practices
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Enable and Shutdown Input (EN/SHDN)

The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply.

While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the SLVSGF4-TPS1641-TPS1641x：40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き 特長 特長 アプリケーション アプリケーション 概要 概要 Table of Contents Table of Contents Revision History Revision History Revision History Revision History Device Comparison Table Device Comparison Table Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Requirements Timing Requirements Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN) Overvoltage Protection (OVP) Overvoltage Protection (OVP) Output Slew Rate and Inrush Current Control (dVdt) Output Slew Rate and Inrush Current Control (dVdt) Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 Internal Current Limit for the TPS16410 and TPS16411 Internal Current Limit for the TPS16410 and TPS16411 Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads Fast-Trip and Short-Circuit Protection Fast-Trip and Short-Circuit Protection Analog Load Current Monitor (IMON) on the IOCP Pin Analog Load Current Monitor (IMON) on the IOCP Pin IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) Thermal Shutdown and Overtemperature Protection Thermal Shutdown and Overtemperature Protection Fault Response and Indication (FLT) Fault Response and Indication (FLT) Device Functional Modes Device Functional Modes Application and Implementation Application and Implementation Application Information Application Information Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Setting Overvoltage Setpoints Setting Overvoltage Setpoints Setting the Output Overcurrent Setpoint (IOCP) Setting the Output Overcurrent Setpoint (IOCP) Setting the Output Power Limit Setting the Output Power Limit Monitoring the Output Current Monitoring the Output Current Limiting the Inrush Current and Setting the Output Slew Rate Limiting the Inrush Current and Setting the Output Slew Rate Application Curves Application Curves System Examples System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Best Design Practices Power Supply Recommendations Power Supply Recommendations Transient Protection Transient Protection Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support ドキュメントの更新通知を受け取る方法 ドキュメントの更新通知を受け取る方法 サポート・リソース サポート・リソース Trademarks Trademarks 静電気放電に関する注意事項 静電気放電に関する注意事項 用語集 用語集 Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要なお知らせと免責事項 重要なお知らせと免責事項 TPS1641x 40V、1.8A 電力および電流制限 eFuse、
入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、
入力と出力の間の短絡検出機能付き 特長 B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 特長 B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B20230421ドキュメント全体を通して新しいデバイス・バリアントの情報を追加yes 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 4.5V～40V (電力制限デバイス)2.7V～40V (電流制限デバイス)出力側で最大 -1V の負電圧に対応非常に小さいオン抵抗RON = 152mΩ (標準値)ON2W～64W の電力制限0.03A～1.8A の電流制限入力と出力の間の短絡を検出し、FLT ピンで通知FLT FLT 出力を診断と外部 PFET の駆動に使用可能 FLT15W 時に ±5% の精度の電力制限 (電力制限デバイス)1A 時に ±6% の精度の電流制限 (電流制限デバイス)構成可能な過電圧保護構成可能な過電流保護 (IOCP)OCP過渡電流のブランキング時間を構成可能外部 FET による最大 60V の過電圧保護突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能イネーブルおよびシャットダウン制御IOCP ピンで出力負荷電流を監視サーマル・シャットダウンによる過熱保護 (OTP)小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) アプリケーション 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム アプリケーション 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 冷蔵庫と冷凍庫 オーブン オーブン 食器洗い機 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 呼吸補助装置 麻酔供給システム 麻酔供給システム 概要 A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 概要 A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes Aデバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no B20230421新しいデバイス・バリアントを追加no TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。FLTFLTこれらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) 部品番号パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm TPS1641x VSON (10) 3.00mm × 3.00mm TPS1641xVSON (10)3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 概略回路図 概略回路図 過渡負荷に対するブランキング時間を構成可能 過渡負荷に対するブランキング時間を構成可能 Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Revision History yes December 2022 April 2023 A B Revision History yes December 2022 April 2023 A B yes December 2022 April 2023 A B yesDecember 2022April 2023AB Revision History yes June 2022 December 2022 * A Revision History yes June 2022 December 2022 * A yes June 2022 December 2022 * A yesJune 2022December 2022*A Device Comparison Table B 20230421 Added new device variants no Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Device Comparison Table B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection Part NumberPower or Current LimitFault BehaviorIN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N TPS16410 Power limit Auto-retry Y TPS16410Power limitAuto-retryY TPS16411 Power limit Latch-off Y TPS16411Power limitLatch-offY TPS16412 Current limit Auto-retry Y TPS16412Current limitAuto-retryY TPS16413 Current limit Latch-off Y TPS16413Current limitLatch-offY TPS16414 Power limit Auto-retry N TPS16414Power limitAuto-retryN TPS16415 Power limit Latch-off N TPS16415Power limitLatch-offN TPS16416 Current limit Auto-retry N TPS16416Current limitAuto-retryN TPS16417 Current limit Latch-off N TPS16417Current limitLatch-offNSee IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) Pin Configuration and Functions B 20230421 Added new device variants no TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power Pin Configuration and Functions B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION PINI/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1DESCRIPTION NAME NO. NAMENO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. IN 1 P Power input for internal FET. IN IN1PPower input for internal FET. Vcc 2 P Supply input for internal circuits of the device. Vcc cc2PSupply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. OVP OVP3IOvervoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. FLT FLT4OActive low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. FLT Pin Indication for Different Events FLT Pin Indication for Different Events FLT Pin Indication for Different EventsFLTFLT EN/SHDN 5 I Enable or shutdown input. EN/SHDN EN/SHDN SHDN5IEnable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. PDLY6I/OTPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. IDLYTPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. dVdT dVdT 7I/OOutput slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. PLIM8I/OTPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. ILIMTPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. IOCP/IMON9I/OOvercurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. OUT10PPower output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PowerPAD/GND—GGND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PowerPAD must be connected to GND of input power supply. PowerPADConnect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Vcc, FLT Input Voltage –0.3 67 V Vcc, FLT ccFLTInput Voltage–0.367V OVP Input Voltage –0.3 62 V OVPInput Voltage–0.362V IN, IN-OUT, IOCP Input Voltage –0.3 42 V IN, IN-OUT, IOCPInput Voltage–0.342V OUT Input Voltage –1 42 V OUTInput Voltage–142V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V EN/SHDN, PDLY/IDLYSHDNInput Voltage–0.35.5V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V dVdT, PLIM/ILIMInput Voltage–0.35.5V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited IIOCP,IPDLY,IPLIM, IdVdT, IILIM IOCPPDLYPLIMdVdTILIMSource CurrentInternally Limited TJ Junction temperature –40 150 °C TJ JJunction temperature–40150°C Transient Junction Temperature –40 TTSD °C Transient Junction Temperature–40TTSD TSD°C Tstg Storage temperature –65 150 °C Tstg stgStorage temperature–65150°C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1±1500V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Vcc Supply voltage VIN 60 V VccSupply voltageVIN IN60V FLT Input Voltage 0 60 V FLT FLTInput Voltage060V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V INInput Voltage (TPS16410, TPS16411, TPS16414, TPS16415)4.540V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V INInput Voltage (TPS16412, TPS16413, TPS16416, TPS16417)2.740V OUT Input Voltage 0 40 V OUTInput Voltage040V EN/SHDN, OVP Input Voltage 0 5.5 V EN/SHDN, OVPSHDNInput Voltage05.5V PDLY/IDLY External capacitor 0.012 10 µF PDLY/IDLYExternal capacitor0.01210µF dVdT External capacitor 0.01 5 µF dVdTExternal capacitor0.015µF IOCP External resistor 6.34 80.6 kΩ IOCPExternal resistor6.3480.6kΩ PLIM External resistor 12.4 412 kΩ PLIMExternal resistor12.4412kΩ ILIM External resistor 5.1 348 kΩ ILIMExternal resistor5.1348kΩ TJ Junction temperature –40 125 °C TJ JJunction temperature–40125°C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1TPS1641UNIT DRC (VSON) DRC (VSON) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJA θJA Junction-to-ambient thermal resistance43.7°C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance50.0°C/W RθJB Junction-to-board thermal resistance 15.8 °C/W RθJB θJBJunction-to-board thermal resistance15.8°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W ΨJB JBJunction-to-board characterization parameter15.8°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance2.1°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted))AJINININILIMPLIM  IOCP   FLTOUTINdVdTSHDN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ OPERATING INPUT AND SUPPLY VOLTAGE OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V Vcc ccOperating Supply voltageVIN IN60V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN INOperating Input voltageTPS16410, TPS16411, TPS16414 ,TPS164154.540V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V VIN INOperating Input voltageTPS16412, TPS16413, TPS16416, TPS164172.740V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQ QOperting Supply curent (Vcc)EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open SHDNccIN ILIM PLIM1.22.1mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IQSD QSDShutdown Supply current (Vcc)EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = OpenSHDNccIN ILIM PLIMIOCP1436µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG INLKGIN Leakage Current in ON StateEN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = OpenSHDNIN ccILIM PLIM0.0250.52mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA IINLKG-SD INLKG-SDIN Leakage Current in ShutdownEN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = OpenSHDNIN ccILIM PLIMIOCP0.72.8µA OVER-VOLTAGE PROTECTION (OVP) INPUT OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPR OVPROVP rising threshold1.481.531.58V VOVPF OVP falling threshold 1.34 1.40 1.46 V VOVPF OVPFOVP falling threshold1.341.401.46V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA IOVP OVPOVP leakage current0 V ≤ VOVP ≤ 4 VOVP –350–265–200nA EN/SHDN INPUT EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENR ENREnable rising threshold1.2V VENF Enable falling threshold 0.59 V VENF ENFEnable falling threshold0.59V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA IEN ENEnable leakage current0 V ≤ VEN ≤ 4 VEN –10µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V VEN-Open EN-OpenOpen circuit Enable VoltageIEN = 0.1 µA, VCC ≥ 5 VENCC 4.9V OUTPUT POWER LIMITING (PLIM) OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT OUTOutput Power LimitRPLIM = 26.7 kΩPLIM33.664.5W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT OUTOutput Power LimitRPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°CPLIMA 12.9413.6914.44W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W POUT OUTOutput Power LimitRPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°CPLIMA 343739.8W OUTPUT CURRENT LIMITING (ILIM) OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT OUTOutput Current LimitRILIM = 332 kΩILIM0.0240.0320.039A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT OUTOutput Current LimitRILIM = 10 kΩ, –40°C ≤ TA ≤ +85°CILIMA 0.9180.9871.035A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A IOUT OUTOutput Current LimitRILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°CILIMA 1.6711.771.881A POWER OUTPUT (OUT) POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON ONIN to OUT On resistance–40°C ≤ TJ ≤ 125°CJ96153260mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON ONIN to OUT On resistance0°C ≤ TJ ≤ 85°CJ153215mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ RON ONIN to OUT On resistanceTJ = 25°CJ153160mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA ILKG-OUT LKG-OUTOutput Leakage current in OFF stateVIN = 40 V, VOUT = 0 V, EN = LowINOUT–15–1.2µA CURRENT MONITORING OUTPUT (IMON) CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A GIMON IMONGain : IMON/IOUT MONOUTIOUT = 0.05 to 1.8 AOUT455055µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OSIMON IMONIMON Offset currentMONIOUT = 0.3 to 0.8 AOUT–0.80.050.8µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP OCPOver curret protection set-pointRIOCP = 7.32 kΩIOCP2.112.232.35A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IOCP OCPOver curret protection set-pointRIOCP = 16.2 kΩIOCP0.951.011.07A IFasttrip Fast Trip protection threshold 1.9 × IOCP A IFasttrip FasttripFast Trip protection threshold1.9 × IOCP OCPA ISCP Short circuit protection threshold 6.7 A ISCP SCPShort circuit protection threshold6.7A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A ILIM-Internal LIM-InternalInternal Current LimitTPS16410, TPS16411, TPS16414, TPS164150.81 × IOCP OCPA THERMAL PROTECTION and SHUTDOWN (TTSD) THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD TSDThermal shutdown temperature155°C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C TTSD-hyst TSD-hystThermal shutdown temperature hysteresis12°C Output slew rate control (dVdT) Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA IdVdT dVdTdVdT charging current1.7822.23µA GdVdT dVdT Gain 50 V/V GdVdT dVdTdVdT Gain50V/V FLT Output (FLTb) (Open Drain Output) FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω RFLTb FLTbFault pin pull down resistance73Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IFLTb-LKG FLTb-LKGFault pin leakage current FLT is High,  V FLT  ≤ 25 VFLT FLT FLT–10.0051µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Rshort shortResistance for IN to OUT short detection30mΩ Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted))AJININCCINENILIMPLIM   IOCP   OUTINdVdT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Enable/SHDN and Vcc Input Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tON_DLY ON_DLYTurn on delay with VCC CCVEN = VENR + 0.1 V , RLOAD = OpenENENR LOAD500µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_ON_DLY EN_ON_DLYEnable on delayFast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = OpenENENR LOAD270µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tEN_OFF_DLY EN_OFF_DLYEnable off delayVEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100EN ENFOUT INLOAD1.2µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms tLOW_SHDN LOW_SHDNMin low pulse for entering shutdownRLOAD = 100LOAD24ms OVP Input OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_ENTRY_DLY OVP_ENTRY_DLYOVP entry delayVOVP = VOVPR + 25 mV to FLT LowOVPOVPRFLT 0.75µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs tOVP_EXIT_DLY OVP_EXIT_DLYOVP exit delayVOVP = VOVPF - 25 mV to to FLT HighOVP OVPFFLT 0.6µs Over Current Protection and Short-circuit protection Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tFASTTRIP_DLY FASTTRIP_DLYFast Trip protection delay IFASTTRIP < IOUT < ISCP to FET OFFFASTTRIPOUTSCP5.65µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns tSCP_DLY SCP_DLYShort-Circuit protection delayIOUT = ISCP + 500 mA to FET OFFOUTSCP280ns Power Limiting Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPDLY PDLYBlanking time before power limitingIOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nFOUTOCPOUT6.5ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-RES PLIM-RESPower Limit response timeIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPENOUTOCPOUT215µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s tPLIM-DUR PLIM-DURPowerLimit Duration2 x tPDLY PDLYs Current Limiting Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tIDLY IDLYBlanking time before current limitingIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nFOUTOCPOUT6.5ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-RES ILIM-RESCurrent Limit response timeIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPENOUTOCPOUT280µs tILIM-DUR Current Limit Duration 2 x tPDLY s tILIM-DUR ILIM-DURCurrent Limit Duration2 x tPDLY PDLYs Auto-Retry and Thermal Shutdown Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s tRETRY RETRYRetry Delay8 x tPDLY PDLYs Output Ramp Control (dVdT) Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs tdVdT dVdTOutput Ramp TimeCdVdT = Open, VIN = VCC = 24 VdVdTINCC 105µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN_OUT_Short_DetectIN to OUT short detection time when FET is ONIN-OUT Short to FLT Low135ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms tIN_OUT_Short_Detect IN_OUT_Short_DetectIN to OUT short detection time when FET is OFFIN-OUT Short to FLT Low20ms Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted))AJILIMPLIMIOCPFLTOUTINdVdT IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V IQ-ON vs Temperature IQ-ON vs TemperatureQ-ON IQSD vs Temperature IQSD vs TemperatureQSD ILKG-VIN vs Temperature ILKG-VIN vs TemperatureLKG-VIN ILKG-VIN-SD vs Temperature ILKG-VIN-SD vs TemperatureLKG-VIN-SD RDS-ON vs Temperature RDS-ON vs TemperatureDS-ON GdVdT vs Temperature GdVdT vs TemperaturedVdT IdVdT vs Temperature IdVdT vs TemperaturedVdT GIMON vs Temperature GIMON vs TemperatureIMON IOCP vs Temperature IOCP vs TemperatureOCP Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 VIN TDLY vs Temperature TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 VIN Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 VIN Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 VIN Detailed Description Overview B 20230421 Added new device variants no The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. Functional Block Diagram Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. Detailed Description Overview B 20230421 Added new device variants no The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. Overview B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults.ONFLTFLTThe TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. FLT Functional Block Diagram Functional Block Diagram Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Enable and Shutdown Input (EN/SHDN)SHDN The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. Low_SHDNQSDccLow_SHDNEN_OFF_dlyEN_ON_dly ENRENF Low_SHDNEN_OFF_dlyEN_ON_dlyLow_SHDNSHDN EN/SHDN in TPS1641x Devices EN/SHDN in TPS1641x DevicesSHDN Turn-On with Enable VIN = 12 V Turn-On with Enable VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 VIN Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response.FLTOVPROVPFFLT OVPFOVPR OVP_entry_dlyOVP_exit_dly OVP Input in TPS1641x OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Overvoltage Protection Response for IN Voltage 12 V to 40 VVcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in .ccFLTFLT Overvoltage (up to 60 V) Protection with External PFET Overvoltage (up to 60 V) Protection with External PFETTo disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). INRUSHOUT S R   =   I I N R U S H C O U T S R   =   I I N R U S H C O U T S R   =   I I N R U S H C O U T SR =  I I N R U S H C O U T I I N R U S H I I N R U S H I I I N R U S H INRUSH C O U T C O U T C C O U T OUTA capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using .dVdt C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   C C d V d t   dVdt =  I d V d t   ×   G d V d t   S R I d V d t   ×   G d V d t   I d V d t I I d V d t dVdt ×   G d V d t     G  G d V d t   dVdt  S R SRThe fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μFINdVdtOUT Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by .OCPILIM I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M I I L I M LIM=  0.984   A R I L I M   0.984   A 0.984 A R I L I M   R I L I M R R I L I M ILIM  × 10 kΩIf the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM.OCPOUTOUTOUTOCPOCPOUTfast-tripOUTOUT Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip Current Limiting for IOUT < IOCP Current Limiting for IOUT < IOCP OUTOCP IOCP ≤ IOUT < Ifast-trip IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripDuring the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents.INOUTOUTTSDILIM-DURILIM-DUR Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Output Current (IOUT) Device Response Output Current (IOUT) Device Response Output Current (IOUT)OUTDevice Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. IOUT < ILIM The device provides current up to ILIM. IOUT < ILIM OUTLIMThe device provides current up to ILIM.LIM ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. ILIM ≤ IOUT < IOCP LIMOUTOCPThe device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. OCPILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripThe device limits current to ILIM for a maximum duration of tILIM-DUR.ILIM-DUR Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. Ifast-trip ≤ IOUT < ISCP fast-tripOUTSCPThe device turns off the internal FET after a delay of tfast-trip. fast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. ISCP ≤ IOUT SCPOUTThe device turns off the internal FET after a delay of tSCP_dly.SCP_dly Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP OCPOUTOUTINOUTOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M P P L I M LIM=  13.82   W 95.3   k Ω 13.82   W 13.82 W 95.3   k Ω 95.3 kΩ ×  R P L I M R R P L I M PLIM illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. OUTOCPOCPOUTfast-trip Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) Power Limiting (IOUT < IOCP) Power Limiting (IOUT < IOCP)OUTOCP Power Limiting (IOCP ≤ IOUT < Ifast-trip) Power Limiting (IOCP ≤ IOUT < Ifast-trip)OCPOUTfast-tripDuring power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. INOUTOUTTSDPLIM-DURPLIM-DUR Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Output Power (POUT) or Output Current (IOUT) Device Response Output Power (POUT) or Output Current (IOUT) Device Response Output Power (POUT) or Output Current (IOUT)OUTOUTDevice Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. POUT < PLIM The device provides power up to PLIM. POUT < PLIMOUTThe device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. PLIM ≤ POUT and IOUT < IOCP PLIM ≤ POUT OUTOUTOCPThe device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR.PLIM-DUR IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripThe device limits current to PLIM for a maximum duration of tPLIM-DUR.PLIM-DUR Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. Ifast-trip ≤ IOUT < ISCP fast-tripOUTSCPThe device turns off the internal FET after a delay of tfast-trip.fast-trip ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. ISCP ≤ IOUT SCPOUTThe device turns off the internal FET after a delay of tSCP_dly.SCP_dly Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP.OCPOCPTPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. OUTOCPOUTOCP Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads OCP In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08.OCP#GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08 I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P I I O C P OCP=  2.25   A R I O C P   2.25   A 2.25 A R I O C P   R I O C P R R I O C P IOCP  × 7.32 kΩIf the IOCP pin is left open or connected to GND, the device turns off the internal FET.The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFFIf IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Blanking Time (IDLY or PDLY)=  6.5   m s 12   n F   6.5   m s 6.5 ms 12   n F   12 nF  × CDLY Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. SCPSCP_dlyIn case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device.fast-tripfast-trip Short-Circuit Response with VIN = 12 V Short-Circuit Response with VIN = 12 VIN Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700.#GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700 I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T I I O U T OUT= V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P V I O C P -   O S I M O N   ×     R I O C P V I O C P V V I O C P IOCP-  O S I M O N   ×     R I O C P O S I M O N   ×     R I O C P O S I M O N O S OS I M O N IMON ×   R I O C P R R I O C P IOCP G I M O N   ×   R I O C P G I M O N G G I M O N IMON ×  R I O C P R R I O C P IOCP IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes B 20230421 Added recommendations for new device variants yes B 20230421 Added recommendations for new device variants yes B20230421Added recommendations for new device variantsyes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect.shortFLT short IN_OUT_Short_DetectAt start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p).FLTFLTFLTIN_OUT_Short_DetectLow_SHDNSWRipple Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 Switching Load Frequency(IRipple / fSW) ≥ 2RippleSW(IRipple / fSW) < 2RippleSW 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 0 to 5 HzTPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 HzTPS16414, TPS16415, TPS16416, or TPS16417TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V IN to OUT Short Detection for VIN = 12 VIN Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN.INOUTOUTJTSDSHDNSHDNLow_SHDNAfter thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry.TSDTSD-hystretry Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Fault Response and Indication (FLT)FLT B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor.FLTFLTFLTSHDNFLT FLT FLTFLTFLT FLT Output in the TPS1641x FLT Output in the TPS1641xFLT FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY FLT Pin Indication for Different EventsFLT Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Event, Condition FLT PinFLTRetry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY Overvoltage protection (VOVP > VOVPR) Low NA NA Overvoltage protection (VOVP > VOVPR) OVPOVPRLowNANA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413)LowNo retry, latch offNo retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY Thermal shutdown (TJ > TTSD)JTSDLow620 ms8 × tPDLY/IDLY PDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeoutLow620 ms8 × tPDLY/IDLY PDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF For overvoltage protection, device turns on the FET as VOVP falls below VOVPF OVPOVPF Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details.SHDNQSDCC Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN)SHDN Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Example Layout Example Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Parameter Value Parameter Value ParameterValue VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms VIN 18 V to 32 V VIN IN18 V to 32 V POUT ≤ 15 W POUT OUT≤ 15 W Overcurrent protection 1 A Overcurrent protection1 A Output capacitance (COUT) 470 μF Output capacitance (COUT)OUT470 μF IINRUSH ≤ 350 mA IINRUSH INRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Blanking time for transients (PDLY)6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected.#GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB#GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 OVP Rising Setpoint= V O V P R   ×   R 1   +   R 2 R 2 V O V P R   ×   R 1   +   R 2 V O V P R V V O V P R OVPR ×  R 1   +   R 2 R 1   +   R 2 R1 + R2 R 2 R2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 OVP Falling Setpoint= V O V P F   ×   R 1   +   R 2 R 2 V O V P F   ×   R 1   +   R 2 V O V P F V V O V P F OVPF ×  R 1   +   R 2 R 1   +   R 2 R1 + R2 R 2 R2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. OCP Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF.#GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9DdVdt I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H I I I N R U S H INRUSH= I d V d t   ×   G d V d t ×   C O U T C d V d t I d V d t   ×   G d V d t ×   C O U T I d V d t I I d V d t dVdt ×  G d V d t G G d V d t dVdt×  C O U T C C O U T OUT C d V d t C d V d t C C d V d t dVdt Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOUT < IOCP)OUTOCP 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip)OCPOUTfast-trip IN to OUT Short Detection with VIN = 24 V IN to OUT Short Detection with VIN = 24 VIN Power-Up Into Short Power-Up Into Short System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. INccDo not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating.Connect the PowerPAD of the device to GND on the PCB.Do not connect the EN/SHDN pin to voltage more than 5 V.SHDN Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411.INUse 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413.INUse VIN ≤ VCC ≤ 60 V.INCCPull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. FLTFLT Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Minimize lead length and inductance into and out of the device.Use a large PCB GND plane.Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output.Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device.Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N IN V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E V V I N - S P I K E IN-SPIKE= V I N V V I N IN+  I L O A D I I L O A D LOAD ×  L I N   C I N L I N   C I N L I N   L I N L L I N IN  C I N C I N C C I N INSome applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Transient Protection with TPS1641xTVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Example Layout Example Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC.INLocate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP RILM or RPLM ILMPLMRIOCP IOCPCDLY DLYCdVdT dVdTResistors for OVPConnect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing.Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC.OUT Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。ti.com サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 TI E2E サポート ・フォーラムTI E2Eリンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。使用条件 Trademarks Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。TI の販売条件ti.com お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated for VENR and VENF thresholds and the SLVSGF4-TPS1641-TPS1641x：40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、入力と出力の間の短絡検出機能付き 特長 特長 アプリケーション アプリケーション 概要 概要 Table of Contents Table of Contents Revision History Revision History Revision History Revision History Device Comparison Table Device Comparison Table Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Requirements Timing Requirements Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN) Overvoltage Protection (OVP) Overvoltage Protection (OVP) Output Slew Rate and Inrush Current Control (dVdt) Output Slew Rate and Inrush Current Control (dVdt) Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 Internal Current Limit for the TPS16410 and TPS16411 Internal Current Limit for the TPS16410 and TPS16411 Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads Fast-Trip and Short-Circuit Protection Fast-Trip and Short-Circuit Protection Analog Load Current Monitor (IMON) on the IOCP Pin Analog Load Current Monitor (IMON) on the IOCP Pin IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) Thermal Shutdown and Overtemperature Protection Thermal Shutdown and Overtemperature Protection Fault Response and Indication (FLT) Fault Response and Indication (FLT) Device Functional Modes Device Functional Modes Application and Implementation Application and Implementation Application Information Application Information Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Setting Overvoltage Setpoints Setting Overvoltage Setpoints Setting the Output Overcurrent Setpoint (IOCP) Setting the Output Overcurrent Setpoint (IOCP) Setting the Output Power Limit Setting the Output Power Limit Monitoring the Output Current Monitoring the Output Current Limiting the Inrush Current and Setting the Output Slew Rate Limiting the Inrush Current and Setting the Output Slew Rate Application Curves Application Curves System Examples System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Best Design Practices Power Supply Recommendations Power Supply Recommendations Transient Protection Transient Protection Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support ドキュメントの更新通知を受け取る方法 ドキュメントの更新通知を受け取る方法 サポート・リソース サポート・リソース Trademarks Trademarks 静電気放電に関する注意事項 静電気放電に関する注意事項 用語集 用語集 Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要なお知らせと免責事項 重要なお知らせと免責事項 TPS1641x 40V、1.8A 電力および電流制限 eFuse、
入力と出力の間の短絡検出機能付き TPS1641x 40V、1.8A 電力および電流制限 eFuse、
入力と出力の間の短絡検出機能付き 特長 B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 特長 B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B 20230421 ドキュメント全体を通して新しいデバイス・バリアントの情報を追加 yes B20230421ドキュメント全体を通して新しいデバイス・バリアントの情報を追加yes 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 出力側で最大 -1V の負電圧に対応 非常に小さいオン抵抗RON = 152mΩ (標準値) 2W～64W の電力制限 0.03A～1.8A の電流制限 入力と出力の間の短絡を検出し、FLT ピンで通知 FLT 出力を診断と外部 PFET の駆動に使用可能 15W 時に ±5% の精度の電力制限 (電力制限デバイス) 1A 時に ±6% の精度の電流制限 (電流制限デバイス) 構成可能な過電圧保護 構成可能な過電流保護 (IOCP) 過渡電流のブランキング時間を構成可能 外部 FET による最大 60V の過電圧保護 突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能 イネーブルおよびシャットダウン制御 IOCP ピンで出力負荷電流を監視 サーマル・シャットダウンによる過熱保護 (OTP) 小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) 動作電圧範囲 (IN)： 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 4.5V～40V (電力制限デバイス) 2.7V～40V (電流制限デバイス) 4.5V～40V (電力制限デバイス)2.7V～40V (電流制限デバイス)出力側で最大 -1V の負電圧に対応非常に小さいオン抵抗RON = 152mΩ (標準値)ON2W～64W の電力制限0.03A～1.8A の電流制限入力と出力の間の短絡を検出し、FLT ピンで通知FLT FLT 出力を診断と外部 PFET の駆動に使用可能 FLT15W 時に ±5% の精度の電力制限 (電力制限デバイス)1A 時に ±6% の精度の電流制限 (電流制限デバイス)構成可能な過電圧保護構成可能な過電流保護 (IOCP)OCP過渡電流のブランキング時間を構成可能外部 FET による最大 60V の過電圧保護突入電流からの保護のために出力スルーレート制御 (dVdt) を調整可能イネーブルおよびシャットダウン制御IOCP ピンで出力負荷電流を監視サーマル・シャットダウンによる過熱保護 (OTP)小型サイズ：QFN 3mm × 3 mm (0.5mm ピッチ) アプリケーション 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム アプリケーション 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 オーブン 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 麻酔供給システム 冷蔵庫と冷凍庫 冷蔵庫と冷凍庫 オーブン オーブン 食器洗い機 食器洗い機 HVAC (空調) バルブおよびアクチュエータの制御 HVAC (空調) バルブおよびアクチュエータの制御 呼吸補助装置 呼吸補助装置 麻酔供給システム 麻酔供給システム 概要 A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 概要 A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no A デバイス・ステータスを「事前情報」から「量産データ」に変更 yes Aデバイス・ステータスを「事前情報」から「量産データ」に変更 yes B 20230421 新しいデバイス・バリアントを追加 no B20230421新しいデバイス・バリアントを追加no TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。 TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。 PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。 TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。 これらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 TPS1641x ファミリは、高精度の電力制限または電流制限機能付きの統合型 eFuse デバイスです。このデバイス・ファミリは、過電流保護、過電圧保護、入力と出力の間の短絡検出、過熱保護機能を内蔵し、堅牢な保護を実現します。TPS16410、TPS16411、TPS16414、および TPS16415 デバイスは、負荷に対して 15W 時に ±5% の電力制限を提供します。また、過渡的な過負荷または過電流イベントに対するブランキング時間を構成可能です。TPS16410、TPS16411、TPS16414、および TPS16415 は、IEC60335 および UL60730 規格に準拠した 15W 電力制限用の低消費電力回路 (LPC) で使用できます。TPS1641x デバイスは、隣接するピンの短絡および GND へのピン短絡フォルトに対する保護機能を備えています。PLC および DCS モジュールのバックプレーン電源保護などのアプリケーションでは、ILIM ピンの抵抗を使用して電流制限を設定します。TPS16412、TPS16413、TPS16416、および TPS16417 デバイスは、負荷に対して 1A 時に ±6% の電流制限を提供します。また、これらのデバイスは dVdT ピンを使用して出力スルーレートを制御し、電源投入時に大きな容量性負荷を充電します。TPS1641x は、入力と出力の間の短絡検出機能を備え、入力と出力の間の短絡を FLT ピンで通知します。FLT ピンは、MCU にデジタル入力として提供するか、外部 PFET を駆動します。FLTFLTこれらのデバイスは、-40℃～+125℃の接合部温度範囲で動作が規定されています。 パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm パッケージ情報 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) 部品番号 パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 本体サイズ (公称) 部品番号パッケージ #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230 #GUID-2FDB0C6F-DE70-4B29-80CD-054FD157EA75/GUID-3653871F-5AF1-4A52-A35A-0F101150B230本体サイズ (公称) TPS1641x VSON (10) 3.00mm × 3.00mm TPS1641x VSON (10) 3.00mm × 3.00mm TPS1641xVSON (10)3.00mm × 3.00mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 概略回路図 過渡負荷に対するブランキング時間を構成可能 概略回路図 概略回路図 過渡負荷に対するブランキング時間を構成可能 過渡負荷に対するブランキング時間を構成可能 Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Revision History yes December 2022 April 2023 A B Revision History yes December 2022 April 2023 A B yes December 2022 April 2023 A B yesDecember 2022April 2023AB Revision History yes June 2022 December 2022 * A Revision History yes June 2022 December 2022 * A yes June 2022 December 2022 * A yesJune 2022December 2022*A Device Comparison Table B 20230421 Added new device variants no Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Device Comparison Table B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection Part Number Power or Current Limit Fault Behavior IN-OUT Short Detection Part NumberPower or Current LimitFault BehaviorIN-OUT Short Detection TPS16410 Power limit Auto-retry Y TPS16411 Power limit Latch-off Y TPS16412 Current limit Auto-retry Y TPS16413 Current limit Latch-off Y TPS16414 Power limit Auto-retry N TPS16415 Power limit Latch-off N TPS16416 Current limit Auto-retry N TPS16417 Current limit Latch-off N TPS16410 Power limit Auto-retry Y TPS16410Power limitAuto-retryY TPS16411 Power limit Latch-off Y TPS16411Power limitLatch-offY TPS16412 Current limit Auto-retry Y TPS16412Current limitAuto-retryY TPS16413 Current limit Latch-off Y TPS16413Current limitLatch-offY TPS16414 Power limit Auto-retry N TPS16414Power limitAuto-retryN TPS16415 Power limit Latch-off N TPS16415Power limitLatch-offN TPS16416 Current limit Auto-retry N TPS16416Current limitAuto-retryN TPS16417 Current limit Latch-off N TPS16417Current limitLatch-offNSee IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended device variants. IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) Pin Configuration and Functions B 20230421 Added new device variants no TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power Pin Configuration and Functions B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16410, TPS16411, TPS16414 and TPS16415 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) TPS16412, TPS16413, TPS16416 and TPS16417 10-Pin DRC VSON Package (Top View) Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. Pin Functions PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. PIN I/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION PINI/O #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 #GUID-7CD8F0E2-2565-41C1-A379-B1DE756A4972/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1DESCRIPTION NAME NO. NAMENO. IN 1 P Power input for internal FET. Vcc 2 P Supply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. IN 1 P Power input for internal FET. IN IN1PPower input for internal FET. Vcc 2 P Supply input for internal circuits of the device. Vcc cc2PSupply input for internal circuits of the device. OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. OVP OVP3IOvervoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. FLT FLT4OActive low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. FLT Pin Indication for Different Events FLT Pin Indication for Different Events FLT Pin Indication for Different EventsFLTFLT EN/SHDN 5 I Enable or shutdown input. EN/SHDN EN/SHDN SHDN5IEnable or shutdown input. PDLY 6 I/O TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. PDLY6I/OTPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. IDLYTPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. dVdT dVdT 7I/OOutput slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM 8 I/O TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. PLIM8I/OTPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. ILIMTPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. IOCP/IMON9I/OOvercurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET. OUT10PPower output from internal FET. PowerPAD/GND — G GND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PowerPAD/GND—GGND connection for the device. PowerPAD must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. PowerPAD must be connected to GND of input power supply. PowerPADConnect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315321/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_1_ABSMAX_FOOTER1 MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C Vcc, FLT Input Voltage –0.3 67 V Vcc, FLT ccFLTInput Voltage–0.367V OVP Input Voltage –0.3 62 V OVPInput Voltage–0.362V IN, IN-OUT, IOCP Input Voltage –0.3 42 V IN, IN-OUT, IOCPInput Voltage–0.342V OUT Input Voltage –1 42 V OUTInput Voltage–142V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V EN/SHDN, PDLY/IDLYSHDNInput Voltage–0.35.5V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V dVdT, PLIM/ILIMInput Voltage–0.35.5V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited IIOCP,IPDLY,IPLIM, IdVdT, IILIM IOCPPDLYPLIMdVdTILIMSource CurrentInternally Limited TJ Junction temperature –40 150 °C TJ JJunction temperature–40150°C Transient Junction Temperature –40 TTSD °C Transient Junction Temperature–40TTSD TSD°C Tstg Storage temperature –65 150 °C Tstg stgStorage temperature–65150°C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 ±1500 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER1±1500V Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 Charged device model (CDM), per JEDEC specification JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315322/A_6534948C_E24A_405C_8CF7_C493A4C1CD37_TPS1641X_SF_UPLOAD_TABLE_2_ESDRATINGS_COMMERCIAL_FOOTER2±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.012 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C Vcc Supply voltage VIN 60 V VccSupply voltageVIN IN60V FLT Input Voltage 0 60 V FLT FLTInput Voltage060V IN Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415) 4.5 40 V INInput Voltage (TPS16410, TPS16411, TPS16414, TPS16415)4.540V IN Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417) 2.7 40 V INInput Voltage (TPS16412, TPS16413, TPS16416, TPS16417)2.740V OUT Input Voltage 0 40 V OUTInput Voltage040V EN/SHDN, OVP Input Voltage 0 5.5 V EN/SHDN, OVPSHDNInput Voltage05.5V PDLY/IDLY External capacitor 0.012 10 µF PDLY/IDLYExternal capacitor0.01210µF dVdT External capacitor 0.01 5 µF dVdTExternal capacitor0.015µF IOCP External resistor 6.34 80.6 kΩ IOCPExternal resistor6.3480.6kΩ PLIM External resistor 12.4 412 kΩ PLIMExternal resistor12.4412kΩ ILIM External resistor 5.1 348 kΩ ILIMExternal resistor5.1348kΩ TJ Junction temperature –40 125 °C TJ JJunction temperature–40125°C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT DRC (VSON) 10 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 TPS1641 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000315335/A_TPS2661X_SF_OTHER_TABLES_4_THERMAL_1PKG_FOOTER1TPS1641UNIT DRC (VSON) DRC (VSON) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJA θJA Junction-to-ambient thermal resistance43.7°C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance50.0°C/W RθJB Junction-to-board thermal resistance 15.8 °C/W RθJB θJBJunction-to-board thermal resistance15.8°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W ΨJB JBJunction-to-board characterization parameter15.8°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance2.1°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Electrical Characteristics –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V (TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open(Allvoltages referenced to GND, (unless otherwise noted))AJINININILIMPLIM  IOCP   FLTOUTINdVdTSHDN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPF OVP falling threshold 1.34 1.40 1.46 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 6.7 A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA GdVdT dVdT Gain 50 V/V FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ OPERATING INPUT AND SUPPLY VOLTAGE OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V Vcc ccOperating Supply voltageVIN IN60V VIN Operating Input voltage TPS16410, TPS16411, TPS16414 ,TPS16415 4.5 40 V VIN INOperating Input voltageTPS16410, TPS16411, TPS16414 ,TPS164154.540V VIN Operating Input voltage TPS16412, TPS16413, TPS16416, TPS16417 2.7 40 V VIN INOperating Input voltageTPS16412, TPS16413, TPS16416, TPS164172.740V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open  1.2 2.1 mA IQ QOperting Supply curent (Vcc)EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open SHDNccIN ILIM PLIM1.22.1mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = Open 14 36 µA IQSD QSDShutdown Supply current (Vcc)EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open, RIOCP = OpenSHDNccIN ILIM PLIMIOCP1436µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.025 0.52 mA IINLKG INLKGIN Leakage Current in ON StateEN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = OpenSHDNIN ccILIM PLIM0.0250.52mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = Open 0.7 2.8 µA IINLKG-SD INLKG-SDIN Leakage Current in ShutdownEN/SHDN = GND,VIN = Vcc = 40 V,  RILIM or RPLIM = Open, RIOCP = OpenSHDNIN ccILIM PLIMIOCP0.72.8µA OVER-VOLTAGE PROTECTION (OVP) INPUT OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.48 1.53 1.58 V VOVPR OVPROVP rising threshold1.481.531.58V VOVPF OVP falling threshold 1.34 1.40 1.46 V VOVPF OVPFOVP falling threshold1.341.401.46V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –350 –265 –200 nA IOVP OVPOVP leakage current0 V ≤ VOVP ≤ 4 VOVP –350–265–200nA EN/SHDN INPUT EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENR ENREnable rising threshold1.2V VENF Enable falling threshold 0.59 V VENF ENFEnable falling threshold0.59V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –10 µA IEN ENEnable leakage current0 V ≤ VEN ≤ 4 VEN –10µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 5 V 4.9 V VEN-Open EN-OpenOpen circuit Enable VoltageIEN = 0.1 µA, VCC ≥ 5 VENCC 4.9V OUTPUT POWER LIMITING (PLIM) OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3 3.66 4.5 W POUT OUTOutput Power LimitRPLIM = 26.7 kΩPLIM33.664.5W POUT Output Power Limit RPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°C 12.94 13.69 14.44 W POUT OUTOutput Power LimitRPLIM = 95.3 kΩ, –40°C ≤ TA ≤ +85°CPLIMA 12.9413.6914.44W POUT Output Power Limit RPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°C 34 37 39.8 W POUT OUTOutput Power LimitRPLIM = 255 kΩ, –40°C ≤ TA ≤ +85°CPLIMA 343739.8W OUTPUT CURRENT LIMITING (ILIM) OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.024 0.032 0.039 A IOUT OUTOutput Current LimitRILIM = 332 kΩILIM0.0240.0320.039A IOUT Output Current Limit RILIM = 10 kΩ, –40°C ≤ TA ≤ +85°C 0.918 0.987 1.035 A IOUT OUTOutput Current LimitRILIM = 10 kΩ, –40°C ≤ TA ≤ +85°CILIMA 0.9180.9871.035A IOUT Output Current Limit RILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°C 1.671 1.77 1.881 A IOUT OUTOutput Current LimitRILIM = 5.49 kΩ, –40°C ≤ TA ≤ +85°CILIMA 1.6711.771.881A POWER OUTPUT (OUT) POWER OUTPUT (OUT) RON IN to OUT On resistance –40°C ≤ TJ ≤ 125°C 96 153 260 mΩ RON ONIN to OUT On resistance–40°C ≤ TJ ≤ 125°CJ96153260mΩ RON IN to OUT On resistance 0°C ≤ TJ ≤ 85°C 153 215 mΩ RON ONIN to OUT On resistance0°C ≤ TJ ≤ 85°CJ153215mΩ RON IN to OUT On resistance TJ = 25°C 153 160 mΩ RON ONIN to OUT On resistanceTJ = 25°CJ153160mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –15 –1.2 µA ILKG-OUT LKG-OUTOutput Leakage current in OFF stateVIN = 40 V, VOUT = 0 V, EN = LowINOUT–15–1.2µA CURRENT MONITORING OUTPUT (IMON) CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 to 1.8 A 45 50 55 µA/A GIMON IMONGain : IMON/IOUT MONOUTIOUT = 0.05 to 1.8 AOUT455055µA/A OSIMON IMON Offset current IOUT = 0.3 to 0.8 A –0.8 0.05 0.8 µA OSIMON IMONIMON Offset currentMONIOUT = 0.3 to 0.8 AOUT–0.80.050.8µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.11 2.23 2.35 A IOCP OCPOver curret protection set-pointRIOCP = 7.32 kΩIOCP2.112.232.35A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.95 1.01 1.07 A IOCP OCPOver curret protection set-pointRIOCP = 16.2 kΩIOCP0.951.011.07A IFasttrip Fast Trip protection threshold 1.9 × IOCP A IFasttrip FasttripFast Trip protection threshold1.9 × IOCP OCPA ISCP Short circuit protection threshold 6.7 A ISCP SCPShort circuit protection threshold6.7A ILIM-Internal Internal Current Limit TPS16410, TPS16411, TPS16414, TPS16415 0.81 × IOCP A ILIM-Internal LIM-InternalInternal Current LimitTPS16410, TPS16411, TPS16414, TPS164150.81 × IOCP OCPA THERMAL PROTECTION and SHUTDOWN (TTSD) THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD TSDThermal shutdown temperature155°C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C TTSD-hyst TSD-hystThermal shutdown temperature hysteresis12°C Output slew rate control (dVdT) Output slew rate control (dVdT) IdVdT dVdT charging current 1.78 2 2.23 µA IdVdT dVdTdVdT charging current1.7822.23µA GdVdT dVdT Gain 50 V/V GdVdT dVdTdVdT Gain50V/V FLT Output (FLTb) (Open Drain Output) FLT Output (FLTb) (Open Drain Output) RFLTb Fault pin pull down resistance 73 Ω RFLTb FLTbFault pin pull down resistance73Ω IFLTb-LKG Fault pin leakage current FLT is High,  V FLT  ≤ 25 V –1 0.005 1 µA IFLTb-LKG FLTb-LKGFault pin leakage current FLT is High,  V FLT  ≤ 25 VFLT FLT FLT–10.0051µA IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413) Rshort Resistance for IN to OUT short detection 30 mΩ Rshort shortResistance for IN to OUT short detection30mΩ Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms –40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. (Allvoltages referenced to GND, (unless otherwise noted))AJININCCINENILIMPLIM   IOCP   OUTINdVdT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-DUR Current Limit Duration 2 x tPDLY s Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms Enable/SHDN and Vcc Input Enable/SHDN and Vcc Input tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs tON_DLY ON_DLYTurn on delay with VCC CCVEN = VENR + 0.1 V , RLOAD = OpenENENR LOAD500µs tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs tEN_ON_DLY EN_ON_DLYEnable on delayFast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = OpenENENR LOAD270µs tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs tEN_OFF_DLY EN_OFF_DLYEnable off delayVEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100EN ENFOUT INLOAD1.2µs tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms tLOW_SHDN LOW_SHDNMin low pulse for entering shutdownRLOAD = 100LOAD24ms OVP Input OVP Input tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_ENTRY_DLY OVP_ENTRY_DLYOVP entry delayVOVP = VOVPR + 25 mV to FLT LowOVPOVPRFLT 0.75µs tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs tOVP_EXIT_DLY OVP_EXIT_DLYOVP exit delayVOVP = VOVPF - 25 mV to to FLT HighOVP OVPFFLT 0.6µs Over Current Protection and Short-circuit protection Over Current Protection and Short-circuit protection tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs tFASTTRIP_DLY FASTTRIP_DLYFast Trip protection delay IFASTTRIP < IOUT < ISCP to FET OFFFASTTRIPOUTSCP5.65µs tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns tSCP_DLY SCP_DLYShort-Circuit protection delayIOUT = ISCP + 500 mA to FET OFFOUTSCP280ns Power Limiting Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms tPDLY PDLYBlanking time before power limitingIOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nFOUTOCPOUT6.5ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs tPLIM-RES PLIM-RESPower Limit response timeIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPENOUTOCPOUT215µs tPLIM-DUR PowerLimit Duration 2 x tPDLY s tPLIM-DUR PLIM-DURPowerLimit Duration2 x tPDLY PDLYs Current Limiting Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms tIDLY IDLYBlanking time before current limitingIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nFOUTOCPOUT6.5ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs tILIM-RES ILIM-RESCurrent Limit response timeIOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPENOUTOCPOUT280µs tILIM-DUR Current Limit Duration 2 x tPDLY s tILIM-DUR ILIM-DURCurrent Limit Duration2 x tPDLY PDLYs Auto-Retry and Thermal Shutdown Auto-Retry and Thermal Shutdown tRETRY Retry Delay 8 x tPDLY s tRETRY RETRYRetry Delay8 x tPDLY PDLYs Output Ramp Control (dVdT) Output Ramp Control (dVdT) tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs tdVdT dVdTOutput Ramp TimeCdVdT = Open, VIN = VCC = 24 VdVdTINCC 105µs IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms tIN_OUT_Short_Detect IN_OUT_Short_DetectIN to OUT short detection time when FET is ONIN-OUT Short to FLT Low135ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms tIN_OUT_Short_Detect IN_OUT_Short_DetectIN to OUT short detection time when FET is OFFIN-OUT Short to FLT Low20ms Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Typical Characteristics –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V –40 °C ≤ TA = TJ ≤ +125 °C, VIN = 4.5 V to 40 V, Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 100 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted))AJILIMPLIMIOCPFLTOUTINdVdT IQ-ON vs Temperature IQSD vs Temperature ILKG-VIN vs Temperature ILKG-VIN-SD vs Temperature RDS-ON vs Temperature GdVdT vs Temperature IdVdT vs Temperature GIMON vs Temperature IOCP vs Temperature Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 V IQ-ON vs Temperature IQ-ON vs TemperatureQ-ON IQSD vs Temperature IQSD vs TemperatureQSD ILKG-VIN vs Temperature ILKG-VIN vs TemperatureLKG-VIN ILKG-VIN-SD vs Temperature ILKG-VIN-SD vs TemperatureLKG-VIN-SD RDS-ON vs Temperature RDS-ON vs TemperatureDS-ON GdVdT vs Temperature GdVdT vs TemperaturedVdT IdVdT vs Temperature IdVdT vs TemperaturedVdT GIMON vs Temperature GIMON vs TemperatureIMON IOCP vs Temperature IOCP vs TemperatureOCP Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Current Limit vs Temperature for TPS16412 and TPS16413 Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 VIN TDLY vs Temperature TDLY vs Temperature Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 VIN Thermal Shutdown Time vs Power Dissipation with VIN = 12 V Thermal Shutdown Time vs Power Dissipation with VIN = 12 VIN Thermal Shutdown Time vs Power Dissipation with VIN = 24 V Thermal Shutdown Time vs Power Dissipation with VIN = 24 VIN Detailed Description Overview B 20230421 Added new device variants no The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. Functional Block Diagram Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. Detailed Description Overview B 20230421 Added new device variants no The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. Overview B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411, TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults.ONFLTFLTThe TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET. FLT Functional Block Diagram Functional Block Diagram Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Feature Description Enable and Shutdown Input (EN/SHDN) The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V Enable and Shutdown Input (EN/SHDN)SHDN The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the for VENR and VENF thresholds and the for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. illustrates the EN/SHDN input in the TPS1641x devices. shows the start-up of the device with enable input. EN/SHDN in TPS1641x Devices Turn-On with Enable VIN = 12 V The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. Low_SHDNQSDccLow_SHDNEN_OFF_dlyEN_ON_dly ENRENF Low_SHDNEN_OFF_dlyEN_ON_dlyLow_SHDNSHDN EN/SHDN in TPS1641x Devices EN/SHDN in TPS1641x DevicesSHDN Turn-On with Enable VIN = 12 V Turn-On with Enable VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 V VIN = 12 VIN Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Overvoltage Protection (OVP) The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response. OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in . Overvoltage (up to 60 V) Protection with External PFET To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the table for VOVPF and VOVPR­ and for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. illustrates the OVP input in TPS1641x devices. shows the overvoltage response.FLTOVPROVPFFLT OVPFOVPR OVP_entry_dlyOVP_exit_dly OVP Input in TPS1641x OVP Input in TPS1641x Overvoltage Protection Response for IN Voltage 12 V to 40 V Overvoltage Protection Response for IN Voltage 12 V to 40 VVcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET transistor and provide protection from 60-V overvoltage at input as shown in .ccFLTFLT Overvoltage (up to 60 V) Protection with External PFET Overvoltage (up to 60 V) Protection with External PFETTo disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Hot Plugin with External PFET for 60-V Input Hot Plugin with External PFET for 60-V Input Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Output Slew Rate and Inrush Current Control (dVdt) During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). S R   =   I I N R U S H C O U T A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using . C d V d t   =   I d V d t   ×   G d V d t   S R The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). INRUSHOUT S R   =   I I N R U S H C O U T S R   =   I I N R U S H C O U T S R   =   I I N R U S H C O U T SR =  I I N R U S H C O U T I I N R U S H I I N R U S H I I I N R U S H INRUSH C O U T C O U T C C O U T OUTA capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using .dVdt C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   =   I d V d t   ×   G d V d t   S R C d V d t   C C d V d t   dVdt =  I d V d t   ×   G d V d t   S R I d V d t   ×   G d V d t   I d V d t I I d V d t dVdt ×   G d V d t     G  G d V d t   dVdt  S R SRThe fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the device will not power up the output. illustrates the output slew rate control in the TPS1641x devices. shows the output slew rate control response of the device. Output Slew Rate Control in the TPS1641x Output Slew Rate Control in the TPS1641x Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μFINdVdtOUT Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by . I L I M =   0.984   A R I L I M     ×   10   k Ω If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM can be calculated by .OCPILIM I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M =   0.984   A R I L I M     ×   10   k Ω I L I M I I L I M LIM=  0.984   A R I L I M   0.984   A 0.984 A R I L I M   R I L I M R R I L I M ILIM  × 10 kΩIf the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT > ILIM. illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM.OCPOUTOUTOUTOCPOCPOUTfast-tripOUTOUT Current Limiting for IOUT < IOCP IOCP ≤ IOUT < Ifast-trip Current Limiting for IOUT < IOCP Current Limiting for IOUT < IOCP OUTOCP IOCP ≤ IOUT < Ifast-trip IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripDuring the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output currents.INOUTOUTTSDILIM-DURILIM-DUR Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Output Current (IOUT) Device Response Output Current (IOUT) Device Response Output Current (IOUT)OUTDevice Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. IOUT < ILIM The device provides current up to ILIM. IOUT < ILIM OUTLIMThe device provides current up to ILIM.LIM ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. ILIM ≤ IOUT < IOCP LIMOUTOCPThe device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. OCPILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripThe device limits current to ILIM for a maximum duration of tILIM-DUR.ILIM-DUR Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. Ifast-trip ≤ IOUT < ISCP fast-tripOUTSCPThe device turns off the internal FET after a delay of tfast-trip. fast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. ISCP ≤ IOUT SCPOUTThe device turns off the internal FET after a delay of tSCP_dly.SCP_dly Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP OCPOUTOUTINOUTOCP P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M =   13.82   W 95.3   k Ω   ×   R P L I M P L I M P P L I M LIM=  13.82   W 95.3   k Ω 13.82   W 13.82 W 95.3   k Ω 95.3 kΩ ×  R P L I M R R P L I M PLIM illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. OUTOCPOCPOUTfast-trip Power Limiting (IOUT < IOCP) Power Limiting (IOCP ≤ IOUT < Ifast-trip) Power Limiting (IOUT < IOCP) Power Limiting (IOUT < IOCP)OUTOCP Power Limiting (IOCP ≤ IOUT < Ifast-trip) Power Limiting (IOCP ≤ IOUT < Ifast-trip)OCPOUTfast-tripDuring power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. summarizes the device behavior for different output power and current. INOUTOUTTSDPLIM-DURPLIM-DUR Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. Output Power (POUT) or Output Current (IOUT) Device Response Output Power (POUT) or Output Current (IOUT) Device Response Output Power (POUT) or Output Current (IOUT)OUTOUTDevice Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. POUT < PLIM The device provides power up to PLIM. POUT < PLIMOUTThe device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. PLIM ≤ POUT and IOUT < IOCP PLIM ≤ POUT OUTOUTOCPThe device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR.PLIM-DUR IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip OCPOUTfast-tripThe device limits current to PLIM for a maximum duration of tPLIM-DUR.PLIM-DUR Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. Ifast-trip ≤ IOUT < ISCP fast-tripOUTSCPThe device turns off the internal FET after a delay of tfast-trip.fast-trip ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly. ISCP ≤ IOUT SCPOUTThe device turns off the internal FET after a delay of tSCP_dly.SCP_dly Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. Internal Current Limit for the TPS16410 and TPS16411 B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP.OCPOCPTPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP. OUTOCPOUTOCP Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads OCP In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08. I O C P =   2.25   A R I O C P     ×   7.32   k Ω If the IOCP pin is left open or connected to GND, the device turns off the internal FET. The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP pin. The resistor value for overcurrent can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08.OCP#GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-A9DDCAA1-1BA5-4DF1-B822-A1084D0ABB08 I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P =   2.25   A R I O C P     ×   7.32   k Ω I O C P I I O C P OCP=  2.25   A R I O C P   2.25   A 2.25 A R I O C P   R I O C P R R I O C P IOCP  × 7.32 kΩIf the IOCP pin is left open or connected to GND, the device turns off the internal FET.The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFF. #GUID-CEE5453C-3447-4C14-B02F-0B8783EC71CF/GUID-7B6743B8-5B89-4D39-B409-D5561E258CFFIf IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into power or current limiting. B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y B l a n k i n g   T i m e   ( I D L Y   o r   P D L Y ) =   6.5   m s 12   n F     ×   C D L Y Blanking Time (IDLY or PDLY)=  6.5   m s 12   n F   6.5   m s 6.5 ms 12   n F   12 nF  × CDLY Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V Fast-Trip and Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device. Short-Circuit Response with VIN = 12 V During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of tSCP_dly. SCPSCP_dlyIn case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds Ifast-trip for a duration of tfast-trip. shows the short-circuit response of the device.fast-tripfast-trip Short-Circuit Response with VIN = 12 V Short-Circuit Response with VIN = 12 VIN Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P Analog Load Current Monitor (IMON) on the IOCP Pin The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700. I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP/IMON pin by using #GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700.#GUID-743F91F2-76AD-49F8-AE6D-FF0DB411EC6F/GUID-EA44A692-6D23-44A1-BE93-D8E476299700 I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T = V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P I O U T I I O U T OUT= V I O C P -   O S I M O N   ×     R I O C P G I M O N   ×   R I O C P V I O C P -   O S I M O N   ×     R I O C P V I O C P V V I O C P IOCP-  O S I M O N   ×     R I O C P O S I M O N   ×     R I O C P O S I M O N O S OS I M O N IMON ×   R I O C P R R I O C P IOCP G I M O N   ×   R I O C P G I M O N G G I M O N IMON ×  R I O C P R R I O C P IOCP IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) B 20230421 Added recommendations for new device variants yes B 20230421 Added recommendations for new device variants yes B 20230421 Added recommendations for new device variants yes B20230421Added recommendations for new device variantsyes TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p). Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the for Rshort and for tIN_OUT_Short_Detect.shortFLT short IN_OUT_Short_DetectAt start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. illustrates the response of device for IN to OUT short. In case of switching loads on output of device, see for recommended device variants based on switching load frequency fSW (in kHz) and ripple load current IRipple (in mAp-p).FLTFLTFLTIN_OUT_Short_DetectLow_SHDNSWRipple Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 Recommended Device Variants Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 Switching Load Frequency (IRipple / fSW) ≥ 2 (IRipple / fSW) < 2 Switching Load Frequency(IRipple / fSW) ≥ 2RippleSW(IRipple / fSW) < 2RippleSW 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 0 to 5 Hz TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 0 to 5 HzTPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 Hz TPS16414, TPS16415, TPS16416, or TPS16417 TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 > 5 HzTPS16414, TPS16415, TPS16416, or TPS16417TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417 IN to OUT Short Detection for VIN = 12 V IN to OUT Short Detection for VIN = 12 VIN Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. Thermal Shutdown and Overtemperature Protection B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry. During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin low for duration more than tLow_SHDN.INOUTOUTJTSDSHDNSHDNLow_SHDNAfter thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to go below [TTSD – TTSD-hyst] and then the device restarts after a delay of tretry.TSDTSD-hystretry Fault Response and Indication (FLT) B 20230421 Added new device variants no FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF Fault Response and Indication (FLT)FLT B 20230421 Added new device variants no B 20230421 Added new device variants no B 20230421 Added new device variants no B20230421Added new device variantsno FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor. FLT Output in the TPS1641x FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and power limit events. summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT ) such that sink current into FLT pin is less than 3 mA. shows the connection diagram for FLT pin with a pullup resistor.FLTFLTFLTSHDNFLT FLT FLTFLTFLT FLT Output in the TPS1641x FLT Output in the TPS1641xFLT FLT Pin Indication for Different Events Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY FLT Pin Indication for Different EventsFLT Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Event, Condition FLT Pin Retry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416 Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Event, Condition FLT PinFLTRetry Delay With IDLY/PDLY = Open or GND for TPS16410, TPS16412, TPS16414, and TPS16416Retry Delay With Capacitor on IDLY/PDLY pin for TPS16410, TPS16412, TPS16414, and TPS16416 Overvoltage protection (VOVP > VOVPR) Low NA NA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY Overvoltage protection (VOVP > VOVPR) Low NA NA Overvoltage protection (VOVP > VOVPR) OVPOVPRLowNANA IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413) Low No retry, latch off No retry, latch off IN to short detection (TPS16410, TPS16411, TPS16412, and TPS16413)LowNo retry, latch offNo retry, latch off Thermal shutdown (TJ > TTSD) Low 620 ms 8 × tPDLY/IDLY Thermal shutdown (TJ > TTSD)JTSDLow620 ms8 × tPDLY/IDLY PDLY/IDLY After current or power limiting timeout Low 620 ms 8 × tPDLY/IDLY After current or power limiting timeoutLow620 ms8 × tPDLY/IDLY PDLY/IDLY For overvoltage protection, device turns on the FET as VOVP falls below VOVPF For overvoltage protection, device turns on the FET as VOVP falls below VOVPF OVPOVPF Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. Device Functional Modes The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details.SHDNQSDCC Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN) Enable and Shutdown Input (EN/SHDN)SHDN Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Example Layout Example Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Application Information TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin. Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs) The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. provides a typical application circuit for 15-W power limiting. 15-W Power Limiting for Low-Power Circuits 15-W Power Limiting for Low-Power Circuits Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Requirements Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Parameter Value Parameter Value ParameterValue VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms VIN 18 V to 32 V VIN IN18 V to 32 V POUT ≤ 15 W POUT OUT≤ 15 W Overcurrent protection 1 A Overcurrent protection1 A Output capacitance (COUT) 470 μF Output capacitance (COUT)OUT470 μF IINRUSH ≤ 350 mA IINRUSH INRUSH ≤ 350 mA Blanking time for transients (PDLY) 6.5 ms Blanking time for transients (PDLY)6.5 ms Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Detailed Design Procedure Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Setting Overvoltage Setpoints Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB and #GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected.#GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_X4M_ZF3_STB#GUID-E1DF5068-A0C0-4FF5-8AE4-A3F3DEF92878/EQUATION-BLOCK_TZV_ZF3_STB O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 O V P   R i s i n g   S e t p o i n t = V O V P R   ×   R 1   +   R 2 R 2 OVP Rising Setpoint= V O V P R   ×   R 1   +   R 2 R 2 V O V P R   ×   R 1   +   R 2 V O V P R V V O V P R OVPR ×  R 1   +   R 2 R 1   +   R 2 R1 + R2 R 2 R2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 O V P   F a l l i n g   S e t p o i n t = V O V P F   ×   R 1   +   R 2 R 2 OVP Falling Setpoint= V O V P F   ×   R 1   +   R 2 R 2 V O V P F   ×   R 1   +   R 2 V O V P F V V O V P F OVPF ×  R 1   +   R 2 R 1   +   R 2 R1 + R2 R 2 R2 Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. Setting the Output Overcurrent Setpoint (IOCP) To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use . For IOCP = 1 A, R4 is selected as 16.2 kΩ. OCP Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Setting the Output Power Limit For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, use. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ. Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Monitoring the Output Current The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using . Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t Limiting the Inrush Current and Setting the Output Slew Rate For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by #GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9D. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF.#GUID-D88A6004-2EF8-434E-BA27-D6801E7DF9FF/GUID-F96B89FD-DCBD-4096-A701-579C6434AF9DdVdt I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H = I d V d t   ×   G d V d t ×   C O U T C d V d t I I N R U S H I I I N R U S H INRUSH= I d V d t   ×   G d V d t ×   C O U T C d V d t I d V d t   ×   G d V d t ×   C O U T I d V d t I I d V d t dVdt ×  G d V d t G G d V d t dVdt×  C O U T C C O U T OUT C d V d t C d V d t C C d V d t dVdt Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Application Curves Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) IN to OUT Short Detection with VIN = 24 V Power-Up Into Short Overvoltage Protection up to 40 V Overvoltage Protection up to 40 V Inrush Current Control for Hot Plugin at Input Inrush Current Control for Hot Plugin at Input Output Short-Circuit Protection Output Short-Circuit Protection 15-W Power Limiting with TPS16410 (IOUT < IOCP) 15-W Power Limiting with TPS16410 (IOUT < IOCP)OUTOCP 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip) 15-W Power Limiting with TPS16410 (IOCP ≤ IOUT < Ifast-trip)OCPOUTfast-trip IN to OUT Short Detection with VIN = 24 V IN to OUT Short Detection with VIN = 24 VIN Power-Up Into Short Power-Up Into Short System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter System Examples Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load. The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. illustrates the application at the output of DC/DC or flyback converter. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Best Design Practices Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating. Connect the PowerPAD of the device to GND on the PCB. Do not connect the EN/SHDN pin to voltage more than 5 V. Use CIN ≥ 10 nF for decoupling Vcc and IN pins. INccDo not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating.Connect the PowerPAD of the device to GND on the PCB.Do not connect the EN/SHDN pin to voltage more than 5 V.SHDN Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Power Supply Recommendations Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411. Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413. Use VIN ≤ VCC ≤ 60 V. Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411.INUse 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413.INUse VIN ≤ VCC ≤ 60 V.INCCPull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA. FLTFLT Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. illustrates the transient protection circuit. Typical methods for addressing transients include: Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output. Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Minimize lead length and inductance into and out of the device.Use a large PCB GND plane.Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output.Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device.Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with . V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N IN V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E = V I N +   I L O A D   ×   L I N   C I N V I N - S P I K E V V I N - S P I K E IN-SPIKE= V I N V V I N IN+  I L O A D I I L O A D LOAD ×  L I N   C I N L I N   C I N L I N   L I N L L I N IN  C I N C I N C C I N INSome applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. Transient Protection with TPS1641x TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Transient Protection with TPS1641xTVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Example Layout Example Layout Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. Layout Guidelines High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. Locate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC.INLocate the following support components close to their connection pins: RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP RILM or RPLM RIOCP CDLY CdVdT Resistors for OVP RILM or RPLM ILMPLMRIOCP IOCPCDLY DLYCdVdT dVdTResistors for OVPConnect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing.Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC.OUT Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。ti.com サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 TI E2E サポート ・フォーラムTI E2Eリンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。使用条件 Trademarks Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。TI の販売条件ti.com お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. Figure 8-1 illustrates the EN/SHDN input in the TPS1641x devices. Figure 8-2 shows the start-up of the device with enable input.
GUID-20211220-SS0I-M4HM-HJPG-9HWNCJFTWJQJ-low.svg Figure 8-1 EN/SHDN in TPS1641x Devices
GUID-20220603-SS0I-HHKS-VWVT-ZHKZGRBFT10N-low.png
VIN = 12 V
Figure 8-2 Turn-On with Enable