JAJSM93B june   2022  – may 2023 TPS1641

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Shutdown Input (EN/SHDN)
      2. 8.3.2  Overvoltage Protection (OVP)
      3. 8.3.3  Output Slew Rate and Inrush Current Control (dVdt)
      4. 8.3.4  Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
      5. 8.3.5  Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
        1. 8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
      6. 8.3.6  Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
      7. 8.3.7  Fast-Trip and Short-Circuit Protection
      8. 8.3.8  Analog Load Current Monitor (IMON) on the IOCP Pin
      9. 8.3.9  IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
      10. 8.3.10 Thermal Shutdown and Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Overvoltage Setpoints
        2. 9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
        3. 9.2.2.3 Setting the Output Power Limit
        4. 9.2.2.4 Monitoring the Output Current
        5. 9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
    4. 9.4 Best Design Practices
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415

The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use Equation 4 to calculate the value of resistor for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A and PLIM < 0.9 × VOUT × IOCP

Equation 4. PLIM= 13.82 W95.3 kΩ × RPLIM

Figure 8-12 illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip.

GUID-20221202-SS0I-Z6CW-ZD06-BSW8ZMX2X7VL-low.pngFigure 8-12 Power Limiting (IOUT < IOCP)
GUID-20221202-SS0I-NFHS-P5KS-N3QJN03MM0GW-low.pngFigure 8-13 Power Limiting (IOCP ≤ IOUT < Ifast-trip)

During power limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR. After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal shutdown. Table 8-2 summarizes the device behavior for different output power and current.

Table 8-2 Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415 Devices
Output Power (POUT) or Output Current (IOUT) Device Response
POUT < PLIM The device provides power up to PLIM.

PLIM ≤ POUT

and IOUT < IOCP		 The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR.
IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR.
Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip.
ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly.