JAJSCP4 December   2016 TPS2065D

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: TJ = TA = 25°C
    6. 7.6 Electrical Characteristics: -40°C ≤ TJ ≤ 125°C
    7. 7.7 Timing Requirements: -40°C ≤ TJ ≤ 125°C
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 FLT
      6. 8.3.6 Output Discharge
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS2065D current limited power switch uses N-channel MOSFETs in applications requiring continuous load current. The device enters constant-current mode when the load exceeds the current limit threshold.

9.2 Typical Application

TPS2065D Typical_application_schematic.gif Figure 22. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the following input parameters:

  1. The TPS2065D operates from a 5 V±0.5V rail.
  2. What is the normal operation current, for example, the maximum allowable current drawn by portable equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current limit of power switch must exceed 900 mA to avoid false trigger during normal operation. For the TPS2065D device, target 1 A continuous output current application.
  3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power switch that must lower it to ensure power switch can protect the up-stream power when overload is encountered at the output of power switch. For the TPS2065D device, the maximum IOS is 1.8 A.

9.2.2 Detailed Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

  1. Normal input operation voltage
  2. Output continuous current
  3. Maximum up-stream power supply output current

9.2.2.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling.

All protection circuits such as the TPS2065D has the potential for input voltage overshoots and output voltage undershoots.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the abrupt reduction of output short circuit current when the device turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the device output is shorted. Applications with large input inductance (for example, connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the device to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the device input aids in both speeding the response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.

Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS2065D has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120 µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF ceramic capacitance on the output. The voltage undershoot should be controlled to less than 1.5 V for 10 µs.

9.2.3 Application Curves

TPS2065D G001_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 5 mΩ
Figure 23. Output Rise / Fall 5 Ω
TPS2065D G003_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 0 Ω
Figure 25. Enable into Output Short
TPS2065D G002_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 100 Ω
Figure 24. Output Rise / Fall 100 Ω
TPS2065D G004_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 50 mΩ
Figure 26. Pulsed Short Applied
TPS2065D G005_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF
Figure 27. Short Applied
TPS2065D G007_SLVSDQ4.gif
VIN = 5 V COUT = 0 µF RLOAD = 50 mΩ
Figure 29. 50-mΩ Short Circuit
TPS2065D G009_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 7.5 Ω
Figure 31. Power Down – Enabled
TPS2065D G006_SLVSDQ4.gif
VIN = 5 V COUT = 0 µF RLOAD = 50 mΩ
Figure 28. Pulsed 1.45-A Load
TPS2065D G008_SLVSDQ4.gif
VIN = 5 V COUT = 150 µF RLOAD = 7.5 mΩ
Figure 30. Power Up – Enabled