SLVSCJ7B March   2014  – July 2015 TPS22969

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, VBIAS = 5.0 V
    6. 6.6 Electrical Characteristics, VBIAS = 2.5 V
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 On/off Control
      2. 7.3.2 Input Capacitor (CIN)
      3. 7.3.3 Output Capacitor (CL)
      4. 7.3.4 VIN and VBIAS Voltage Range
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VIN to VOUT Voltage Drop
        2. 8.2.2.2 Inrush Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section will highlight some of the design considerations when implementing this device in various applications. A PSPICE model for this device is also available in the product page of this device.

8.2 Typical Application

This application demonstrates how the TPS22969 can be used to power downstream modules with large capacitances. The example below is powering a 100-µF capacitive output load.

TPS22969 app_sch_slvscj7.gifFigure 27. Typical Application Schematic for Powering a Downstream Module

8.2.1 Design Requirements

For this design example, use Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 1.05 V
VBIAS 5.0 V
Load current 6 A

8.2.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

  • VIN voltage
  • VBIAS voltage
  • Load current

8.2.2.1 VIN to VOUT Voltage Drop

The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the device in the Electrical Characteristics, VBIAS = 5.0 V tables of this datasheet. Once the RON of the device is determined based upon the VIN and VBIAS conditions, use Equation 1 to calculate the VIN to VOUT voltage drop:

Equation 1. TPS22969 eq1_delta_slvsci4.gif

where

  • ΔV = voltage drop from VIN to VOUT
  • ILOAD = load current
  • RON = on-resistance of the device for a specific VIN and VBIAS combination

An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.

8.2.2.2 Inrush Current

To determine how much inrush current will be caused by the CL capacitor, use Equation 2:

Equation 2. TPS22969 Eq2_Iinrush_slvsci4.gif

where

  • IINRUSH = amount of inrush caused by CL
  • CL = capacitance on VOUT
  • dt = time it takes for change in VOUT during the ramp up of VOUT when the device is enabled
  • dVOUT = change in VOUT during the ramp up of VOUT when the device is enabled

An appropriate CL value should be placed on VOUT such that the IMAX and IPLS specifications of the device are not violated.

TPS22969 ST_049_SLVSCJ7.pngFigure 28. Inrush current (VBIAS = 5 V, VIN = 1.05 V, CL = 100 µF)

Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 3.

Equation 3. TPS22969 eq_thrm_slvsci4.gif

where

  • PD(max) = maximum allowable power dissipation
  • TJ(max) = maximum allowable junction temperature (125°C for the TPS22969)
  • TA = ambient temperature of the device
  • ΘJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly dependent upon board layout.

8.2.3 Application Curves

TPS22969 SW_016_SW_018_SLVSCJ7.png
VBIAS = 5 V VIN = 5 V CIN = 1 µF
CL = 0.1 µF
Figure 29. tR at VBIAS = 5V
TPS22969 SW_051_SW_053_SLVSCJ7.png
VBIAS = 2.5 V VIN = 2.5 V CIN = 1 µF
CL = 0.1 µF
Figure 31. tR at VBIAS = 2.5 V
TPS22969 SW_017_SW_019_SLVSCJ7.png
VBIAS = 5 V VIN = 5 V CIN = 1 µF
CL = 0.1 µF
Figure 33. tF at VBIAS = 5 V
TPS22969 SW_052_SW_054_SLVSCJ7.png
VBIAS = 2.5 V VIN = 2.5 V CIN = 1 µF
CL = 0.1 µF
Figure 35. tF at VBIAS = 2.5 V
TPS22969 SW_076_SW_078_SLVSCJ7.png
VBIAS = 5 V VIN = 1.05 V CIN = 1 µF
CL = 0.1 µF
Figure 30. tR at VBIAS = 5 V
TPS22969 SW_081_SW_083_SLVSCJ7.png
VBIAS = 2.5 V VIN = 1.05 V CIN = 1 µF
CL = 0.1 µF
Figure 32. tR at VBIAS = 2.5V
TPS22969 SW_052_SW_054_SLVSCJ7.png
VBIAS = 5 V VIN = 2.5 V CIN = 1 µF
CL = 0.1 µF
Figure 34. tF at VBIAS = 5 V
TPS22969 SW_097_SW_099_SLVSCJ7.png
VBIAS = 2.5 V VIN = 0.8 V CIN = 1 µF
CL = 0.1 µF
Figure 36. tF at VBIAS = 2.5 V