7.3.1 Current Limit

Figure 1 shows a simplified view of the TPS22981 current limit function. Both the high-voltage supply current limit and the V3P3 supply current limit are adjustable by external resistors.

Figure 1. Simplified Current Limit Diagram

The current I_{REF_HV} and I_{REF_V3P3} that set the current limit threshold are set with three external resistors as shown in Figure 2. When the TPS22981 is passing the V3P3 voltage, the current limit is set by R_{SET_V3P3}. The VHV path has two modes that allow setting two different current limits. The S0 pin determines which current limit is used. When S0 is asserted high, R_{SET_S0} sets the current limit. When S0 is low, R_{SET_S3} sets the current limit. This allows the system to have two separate VHV current limits for different modes such as active and sleep.

Figure 2. External R_SET Resistance to Set Current Limits

7.3.2 Current Limit Threshold

Figure 3. I_LIM vs R_SET for VHV and V3P3

Figure 4. % Variance from Minimum I_LIM vs R_SET

Figure 3 shows the minimum, typical, and maximum current limit for either supply versus its corresponding R_SET value. Equation 1 is used to determine the RSET needed to set a typical I_LIM for a given supply and mode. Figure 4 shows the percent variation from the typical I_LIM value to the minimum and maximum I_LIM values.

SPACE

Equation 1.

where

• R_SET = external resistor used to set the current limit for V3P3, VHV (S0), or VHV (S3)
• I_LIMTYP = typical current limit for V3P3, VHV (S0), or VHV (S3) set by the external R_SET resistor.

SPACE

Each resistor is placed between the corresponding ISET pin and GND, as shown in Figure 2, providing a minimum current limit between 100mA and 1.5A. For a given R_SET the minimum current limit and the maximum current limit are determined by Equation 2 and Equation 3.

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Equation 2.

SPACE

Equation 3.

7.3.3 Maximum Current Limit Threshold

The TPS22981 has a maximum current limit I_LIMVHVMAX and I_LIM3P3MAX. This prevents excessive current in the case of an ISET pin being shorted to ground.

7.3.4 Transition Delays

Output transitions of the TPS22981 voltages are shown in Figure 5. When the device transitions from V_HV to V_3P3 at the output, the power switches both turn off until the output falls to near the V_3P3 voltage. During this time, a discharge current of I_DIS pulls OUT down. If a load is also pulling current from OUT, the output will drop to near 0 V due to the switch OFF-time of T_3P3OFF.

Figure 5. Output Voltage Transitions (Timing Transitions are 10% to > 90%)

7.3.5 Digital Control Signals

The voltage at OUT is controlled by two input digital logic signals, EN and HV_EN. HV_EN controls the state of the VHV switch and EN controls the state of V3P3 switch. Table 1 lists the possible output states given the conditions of the digital logic signals and the device is not in UVLO. See Table 2 for a more complete description including both UVLO conditions.

Figure 6 shows possible combinations of EN and HV_EN controlling OUT of the TPS22981.

Figure 6. Logic Waveforms Displaying the Transition Between VHV and V3P3

7.3.6 Overcurrent Limit and Short-Circuit Protection

When the load at OUT attempts to draw more current than the limit set by the external R_SET resistors for the V3P3 switch and VHV switch (for both S0 and S3 modes), the device will operate in a constant-current mode while lowering the output voltage. Figure 7 shows the delay, t_LIM, which occurs from the instance an overcurrent fault is detected until the output current is lowered to I_LIMHV tolerances for VHV or I_LIM3V3 tolerances for V3P3 shown in Figure 3. Figure 8 shows the response time versus a resistance shorted across the output.

Figure 7. Overcurrent Output Response

Figure 8. Overcurrent Response Time vs Short Resistance

All short-circuit conditions are treated as overcurrent conditions. In the event of a short circuit, the device will limit the output current to the corresponding R_SET value and continue to do so until thermal shutdown is encountered or the short-circuit condition is removed.

7.3.7 Reverse Current Protection

Reverse current protection for the V3P3 supply to OUT triggers at I_REV3P3 causing the V3P3 supply switch to open. When the HV_EN signal is not asserted and reverse current protection is triggered, a discharge current source is turned on to bring the output voltage to near the V3P3 voltage.

7.3.8 Reverse Current Blocking

The VHV switch blocks reverse current flow from OUT to VHV when the switch is off.

7.3.9 Thermal Shutdown

The device enters thermal shutdown when junction temperature reaches T_SD. The device will resume previous state on power up once the junction temperature has dropped by 10°C. Connect thermal vias to the exposed GND pad underneath the device package for improved thermal diffusion.

7.4.1 UVLO and Enable

When ENHVU is low, the TPS22981 is enabled by the logical AND of the EN input, the V3P3 UVLO, and the Thermal Shutdown. When the V3P3 UVLO threshold has been crossed, the device is not in thermal shutdown, and the EN input is high, the device will enable. When the V3P3 UVLO triggers, regardless of the states of any digital logic controls, the device will open all switches.

ENHVU adds the VHV UVLO to the logical decision enabling the device. When ENHVU is high, the TPS22981 is enabled by the logical AND of the EN input, the V3P3 UVLO, the VHV UVLO, and the thermal shutdown. When both UVLO thresholds have been crossed, the device is not in thermal shutdown, and the EN input is high, the device will enable. When either UVLO triggers, regardless of the states of any digital logic controls, the device will open all switches. Table 2 shows the pin and voltage configurations for enabling the device.

7.4.2 FAULTZ Output

The TPS22981 has an open-drain FAULTZ output. When the device is in a fault condition, the FAULTZ output will pull low. Connect FAULTZ through a pullup resistance to V3P3. A Fault occurs during any of the following conditions.

• EN = 1 and V3P3 is in UVLO (device enabled and V3P3 is in an undervoltage condition)
• EN = 1 and in thermal shutdown condition
• EN = 1, HV_EN = 1, and VHV is in UVLO (device enabled, high voltage enabled, and VHV is in an undervoltage condition)

Table 3 shows these conditions and the resulting FAULTZ output. Note, when V3P3 is below the UVLO threshold, FAULTZ will be 0 when EN=1 or 1 when EN=0. However, when V3P3 falls below V_FAULTZVAL, the FAULTZ output is unknown.

TI recommends that the pullup resistance on FAULTZ be 100 kΩ and must be greater than or equal to 30 kΩ.