SLVSBM6B December   2012  – November 2015 TPS22981

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Current Limit Threshold
      3. 7.3.3 Maximum Current Limit Threshold
      4. 7.3.4 Transition Delays
      5. 7.3.5 Digital Control Signals
      6. 7.3.6 Overcurrent Limit and Short-Circuit Protection
      7. 7.3.7 Reverse Current Protection
      8. 7.3.8 Reverse Current Blocking
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO and Enable
      2. 7.4.2 FAULTZ Output
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Inductive Bounce
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGP Package
VQFN With Exposed Thermal Pad
Top View
TPS22981 pinout_top_SLVSBM6.gif
RGP Package
VQFN With Exposed Thermal Pad
Bottom View
TPS22981 pinout_bot_SLVSBM6.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
EN 5 I Device active-high enable.
ENHVU 16 I Enable VHV UVLO control of device enable. When asserted high, both V3P3 and VHV must be present for device enable. When low, only V3P3 must be present for device enable.
FAULTZ 4 O Fault condition output. This pin is an open-drain pulldown indicating a fault condition. Place a pullup resistance (RFAULTZ) between this pin and V3P3. Float pin or tie pin to GND if unused.
GND 1, 2, 3, 13, 15 P Device ground. All GND pins must be connected to board ground.
GND EP P Exposed pad must be connected to device GND.
HV_EN 11 I Active-high voltage output enable.
ISET_S0 10 I Sets the current limit for VHV in S0 mode. Place resistor between this pin and GND. See Equation 1 to calculate resistor value.
ISET_S3 9 I Sets the current limit for VHV in S3 mode. Place resistor between this pin and GND. See Equation 1 to calculate resistor value.
ISET_V3P3 8 I Sets the current limit for V3P3. Place resistor between this pin and GND. See Equation 1 to calculate resistor value.
OUT 12, 14 O Power output. Place a minimum of 1-µF capacitor to GND as close to this pin as possible.
S0 17 I When this pin is asserted, the device is put in S0 mode. Otherwise the device operates in S3 mode.
V3P3 19, 20 P 3.3-V power supply input. Place a minimum of 0.1-µF capacitor to GND as close to this pin as possible.
V3P3OUT 18 O 3.3-V bypass output. When ENHVU is low, this path is enabled by EN and the V3P3 UVLO. When ENHVU is high, this path is enabled by EN and both the V3P3 UVLO and the VHV UVLO. Place a minimum 0.1-uF capacitor to GND as close to this pin as possible.
VHV 6, 7 P High voltage power supply input. See the Input Inductive Bounce section for more information.