JAJSF18A December   2017  – January 2019 TPS23523

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Relationship between Sense Voltage, Gate Current, and Timer
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
        1. 8.3.1.1 Programming the CL Switch-Over Threshold
        2. 8.3.1.2 Setting Up the PROG Pin
        3. 8.3.1.3 Programming CL1
        4. 8.3.1.4 Programming CL2
      2. 8.3.2 Soft Start Disconnect
      3. 8.3.3 Timer
      4. 8.3.4 Gate 2
      5. 8.3.5 OR-ing
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF State
      2. 8.4.2 Insertion Delay State
      3. 8.4.3 Start-up State
      4. 8.4.4 Normal Operation State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting RSNS
        2. 9.2.2.2  Selecting Soft Start Setting: CSS and CSS,VEE
        3. 9.2.2.3  Selecting VDS Switch Over Threshold
        4. 9.2.2.4  Timer Selection
        5. 9.2.2.5  MOSFET Selection and SOA Checks
        6. 9.2.2.6  Input Cap, Input TVS, and OR-ing FET selection
        7. 9.2.2.7  EMI Filter Consideration
        8. 9.2.2.8  Undervoltage and Overvoltage Settings
        9. 9.2.2.9  Choosing RVCC and CVCC
        10. 9.2.2.10 Power Good Interface to Downstream DC/DC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PW Package
16-Pin (TSSOP)
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
Neg48 1 I Input to the OR-ing controller for the –48 feed. The TPS23523 will regulate the drop from VEE to Neg48 to 25 mV to mimic an ideal diode.
NC 2 No connect to space high voltage pins.
GATE2 3 O Gate driver for the 2nd hot swap FET. NC if feature isn’t used.
BGATE 4 O Gate driver for the OR-ing FET.
VEE 5 GND This pin corresponds to the IC GND. Kelvin sense to the bottom of RSNS to ensure accurate current limit.
SNS 6 I Sense pin, used to measure current and regulate it. Kelvin Sense to RSNS to ensure accurate current limits.
GATE 7 O Gate drive for the main hot swap FET.
SS 8 O Pin used for soft starting the output. Connect a capacitor (CSS) between the SS pin and -48V_OUT. The dv/dt rate on the -48V_OUT pin is proportional to the gate sourcing current divided by CSS.
D 9 I Pin used to sense the drain of the hot swap FET and to program the threshold where the hot swap switches from the CL1 and CL2. Connect a resistor from this pin to the drain of the hot swap FET (also called -48V_OUT) to program the threshold.
TMR 10 O Timer pin used to program the duration when the hot swap FET can be in current limit. Program this time by adding a capacitor between the TMR pin and VEE.
OV 11 I Input overvoltage comparator. Tie a resistor divider to program the threshold where the device turns off due to overvoltage event.
UVEN 12 I Input undervoltage comparator. Tie a resistor divider to program the threshold where the device turns on.
VCC 13 S Clamped supply. Tie to RTN through resistor.
PGb 14 O Power Good Bar, which is an open drain output that indicated when the power is good and the load can start drawing full power. PGb goes low when the hot swap is fully on and the DC/DC can draw full power.
PROG 15 I Adjust current limit and fast trip threshold by tying to VEE, floating, or tying to VEE through resistor.
Vref 16 O 5V reference output. Connect to the base of a BJT to generate a rail that can be used to power current monitors and digital Isolators.