JAJSC25I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Detailed Pin Description
      2. 8.1.2 I2C Detailed Pin Description
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detection Resistance Measurement
      2. 8.3.2  Physical Layer Classification
      3. 8.3.3  Class and Detect Fields
      4. 8.3.4  Register State Following a Fault
      5. 8.3.5  Disconnect
      6. 8.3.6  Disconnect Threshold
      7. 8.3.7  Fast Shutdown Mode
      8. 8.3.8  Legacy Device Detection
      9. 8.3.9  VPWR Undervoltage and UVLO Events
      10. 8.3.10 Timer-Deferrable Interrupt Support
      11. 8.3.11 A/D Converter and I2C Interface
      12. 8.3.12 Independent Operation when the AUTO Bit is Set
      13. 8.3.13 I2C Slave Address and AUTO Bit Programming
    4. 8.4 Device Functional Modes
      1. 8.4.1 Off
      2. 8.4.2 Manual
      3. 8.4.3 Semi-Auto
      4. 8.4.4 Auto
      5. 8.4.5 Push-Button Power On Response
      6. 8.4.6 TSTART Indicators of Detect and Class Failures
      7. 8.4.7 Device Power On Initialization
    5. 8.5 Register Map – I2C-Addressable
      1. 8.5.1  Interrupt Register
      2. 8.5.2  Interrupt Enable Register
      3. 8.5.3  Power Event Register
      4. 8.5.4  Detection Event Register
      5. 8.5.5  Fault Event Register
      6. 8.5.6  Start/ILIM Event Register
      7. 8.5.7  Supply Event Register
      8. 8.5.8  Port n Status Register
        1. 8.5.8.1 Port 1 Status Register
        2. 8.5.8.2 Port 2 Status Register
        3. 8.5.8.3 Port 3 Status Register
        4. 8.5.8.4 Port 4 Status Register
      9. 8.5.9  Power Status Register
      10. 8.5.10 I2C Slave Address Register
      11. 8.5.11 Operating Mode Register
      12. 8.5.12 Disconnect Enable Register
      13. 8.5.13 Detect/Class Enable Register
      14. 8.5.14 Port Power Priority Register
      15. 8.5.15 Timing Configuration Register
      16. 8.5.16 General Mask 1 Register
      17. 8.5.17 Detect/Class Restart Register
      18. 8.5.18 Power Enable Register
      19. 8.5.19 Reset Register
      20. 8.5.20 Legacy Detect Mode Register
      21. 8.5.21 Two-Event Classification Register
      22. 8.5.22 Interrupt Timer Register
      23. 8.5.23 Disconnect Threshold Register
        1. 8.5.23.1 Bits Description
      24. 8.5.24 ICUTnm CONFIG Register
        1. 8.5.24.1 ICUT21 CONFIG Register
        2. 8.5.24.2 ICUT43 CONFIG Register
        3. 8.5.24.3 Bits Description
      25. 8.5.25 Temperature Register
      26. 8.5.26 Input Voltage Register
      27. 8.5.27 Port n Current Register
        1. 8.5.27.1 Port 1 Current Register
        2. 8.5.27.2 Port 2 Current Register
        3. 8.5.27.3 Port 3 Current Register
        4. 8.5.27.4 Port 4 Current Register
      28. 8.5.28 Port n Voltage Register
        1. 8.5.28.1 Port 1 Voltage Register
        2. 8.5.28.2 Port 2 Voltage Register
        3. 8.5.28.3 Port 3 Voltage Register
        4. 8.5.28.4 Port 4 Voltage Register
      29. 8.5.29 PoE Plus Register
      30. 8.5.30 Firmware Revision Register
      31. 8.5.31 I2C Watchdog Register
      32. 8.5.32 Device ID Register
      33. 8.5.33 Cool Down/Gate Drive Register
      34. 8.5.34 Port n Detect Resistance Register
        1. 8.5.34.1 Port 1 Detect Resistance Register
          1. 8.5.34.1.1 Port 2 Detect Resistance Register
          2. 8.5.34.1.2 Port 3 Detect Resistance Register
          3. 8.5.34.1.3 Port 4 Detect Resistance Register
      35. 8.5.35 Port n Detect Voltage Difference Register
        1. 8.5.35.1 Port 1 Detect Voltage Difference Register
        2. 8.5.35.2 Port 2 Detect Voltage Difference Register
        3. 8.5.35.3 Port 3 Detect Voltage Difference Register
        4. 8.5.35.4 Port 4 Detect Voltage Difference Register
      36. 8.5.36 Reserved Registers
  9. 9 Application and Implementation
    1. 9.1 Introduction to PoE
    2. 9.2 Application Information
      1. 9.2.1 Kelvin Current Sensing Resistor
      2. 9.2.2 Connections on Unused Ports
    3. 9.3 Typical Application
      1. 9.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 9.3.1.1 Design Requirements
      2. 9.3.2 Four Port, Auto Mode Application
        1. 9.3.2.1 Design Requirements
      3. 9.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 9.3.3.1 Design Requirements
      4. 9.3.4 Detailed Design Procedure
        1. 9.3.4.1 Power Pin Bypass Capacitors
        2. 9.3.4.2 Per Port Components
        3. 9.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 9.3.5 Application Curves
    4. 9.4 System Examples
      1. 9.4.1 Overcurrent and Overload Protection
      2. 9.4.2 Inrush Protection
      3. 9.4.3 ICUT Current Limit
      4. 9.4.4 Foldback Protection (ILIM)
      5. 9.4.5 Kelvin Current Sensing Resistor
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
    3. 10.3 VPWR-RESET Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB (SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating registers loaded with default values (unless otherwise noted)
MIN TYP MAX UNIT
fSCL SCL clock frequency 10 400 kHz
tLOW LOW period of SCL clock 1.3 µs
tHIGH HIGH period of SCL clock 0.6 µs
tfo SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10-kΩ pullup to 3.3 V 21 250 ns
SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3-kΩ pullup to 3.3 V 60 250 ns
CI2C SCL capacitance 10 pF
CI2C_SDA SDAI, SDAO capacitance 6 pF
tSU,DATW Data set-up time (write operation) 100 ns
tSU,DATR Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, Cb = 400 pF, 1.3-kΩ pull up to 3.3 V 600 ns
tHD,DATW Data hold time (write operation) 0 ns
tHD,DATR Data hold time (read operation) 150 600 ns
tfSDA Input fall times of SDAI, 2.3 → 0.8 V 20 250 ns
trSDA Input rise times of SDAI, 0.8 → 2.3 V 20 300 ns
tr Input rise time of SCL, 0.8 → 2.3 V 20 300 ns
tf Input fall time of SCL, 2.3 → 0.8 V 20 200 ns
tBUF Bus free time between a stop and start condition 1.3 µs
tHD,STA Hold time after (repeated) start condition 0.6 µs
tSU,STA Repeated start condition set-up time 0.6 µs
tSU,STO Stop condition set-up time 0.6 µs
tFLT_INT(1) Fault to INT assertion, Time to internally register an interrupt in response to a fault 150 µs
tARA_INT ARA to INT negation 500 ns
tDG Suppressed spike pulse width, SDAI and SCL 50 ns
tRDG RESET input minimum pulse width (deglitch time) 5 µs
tWDT_I2C I2C Watchdog trip delay 1.1 2.2 3.3 s
tSTP_AOUT Delay STOP bit to AOUT high during I2C address programming 1.25 µs
(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.
TPS23861 fig2_lusba4.gifFigure 1. I2C Timings