SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 17h with 1 Data Byte, Read/Write
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTEN | – | nbitACC | MbitPrty | CLCHE | DECHE | – | – |
| R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INTEN | R/W | 1 | INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no impact on the event registers. 1 = Any unmasked bit of Interrupt register can activate the INT output 0 = INT output cannot be activated |
| 6 | – | R/W | 0 | |
| 5 | nbitACC | R/W | 0 | Register Access Configuration bit. Used to select configuration A or B. 1 = Configuration B. This means 16-bit access with a single device address. 0 = Configuration A. This means 8-bit access, while the 8-port device is treated as 2 separate 4-port devices with 2 consecutive slave addresses. |
| 4 | MbitPrty | R/W | 0 | Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown priority. 1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for port priority and OSS action. 0 = 1-bit shutdown priority. Register 0x15 needs to be followed for port priority and OSS action |
| Note: If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input is in the idle (low) state for a minimum of 200 µsec prior to setting the MbitPrty bit, to avoid any port misbehavior related to loss of synchronization with the OSS bit stream. | ||||
| 3 | CLCHE | R/W | 0 | Class change Enable bit. When set, the CLSCn bits in Detection Event register only indicates when the result of the most current classification operation differs from the result of the previous one. 1 = CLSCn bit is set only when a change of class occurred for the associated port. 0 = CLSCn bit is set each time a classification cycle occurred for the associated port. |
| 2 | DECHE | R/W | 0 | Detect Change Enable bit. When set, the DETCn bits in Detection Event register only indicates when the result of the most current detection operation differs from the result of the previous one. 1 = DETCn bit is set only when a change in detection occurred for the associated port. 0 = DETCn bit is set each time a detection cycle occurred for the associated port. |
| 1 | – | R/W | 0 | |
| 0 | – | R/W | 0 |