SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A1-4 | 48–51 | I | I2C A1-A4 address lines. These pins are internally pulled up to VDD. |
AGND | 21 | — | Analog ground. Connect to GND plane and exposed thermal pad. |
ATST_DCPL0 | 20 | O | Used for internal test purposes, no bypass capacitor is needed. |
DGND | 46 | — | Digital ground. Connect to GND plane and exposed thermal pad. |
DRAIN1-8 | 3, 5, 10, 12, 31, 33, 38, 40 | I | Port 1-8 output voltage monitor. |
DTST_DCPL1 | 47 | O | Used for internal test purposes, no bypass capacitor is needed. |
GAT1-8 | 1, 7, 8, 14, 29, 35, 36, 42 | O | Port 1-8 gate drive output. |
INT | 45 | O | Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This output is open-drain. |
KSENSA/B | 4, 11 | I | Kelvin point connection for SEN1-4 |
KSENSC/D | 32, 39 | I | Kelvin point connection for SEN5-8 |
NC | 15, 16, 18, 19 | O | No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage gradient from VPWR. Leave open. |
22 | — | No connect pin. Leave open. | |
OSS | 56 | I | Port 1-8 fast shutdown. This pin is internally pulled down to DGND. |
Thermal pad | — | — | The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation. |
RESET | 44 | I | Reset input. When asserted low, the TPS2388 is reset. This pin is internally pulled up to VDD. |
Resv | 27, 28, 52 | — | Reserved. No connect pins. Leave open. |
SCL | 53 | I | Serial clock input for I2C bus. |
SDAI | 54 | I | Serial data input for I2C bus. This pin can be connected to SDAO for non-isolated systems. |
SDAO | 55 | O | Serial data output for I2C bus. This pin can be connected to SDAI for non-isolated systems. This output is open-drain. |
SEN1-8 | 2, 6, 9, 13, 30, 34, 37, 41 | I | Port 1-8 current sense input. |
TEST0-3 | 23, 24, 25, 26 | I/O | Used internally for test purposes only. Leave open. |
VDD | 43 | — | Digital supply. Bypass with 0.1 µF to DGND pin. |
VPWR | 17 | — | Analog 48-V positive supply. Bypass with 0.1 µF to AGND pin. |