SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 1Ah with 1 Data Byte, Write Only
Push button register.
Writing a 1 at a bit location triggers an event while a 0 has no impact. Self-clearing bits.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRAIN | CLINP | – | RESAL | RESP4 | RESP3 | RESP2 | RESP1 |
W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLRAIN | W | 0 | Clear all interrupts bit. Writing a 1 to CLRAIN clears all event registers and all bits in the Interrupt register. It also releases the INT pin |
6 | CLINP | W | 0 | When set, it releases the INT pin without any impact on the Event registers nor on the Interrupt register. |
5 | – | W | 0 | |
4 | RESAL | W | 0 | Reset all bits when RESAL is set. Results in a state equivalent to a power-up reset. Note that the VDUV and VPUV bits (Supply Event register) follow the state of VDD and VPWR supply rails. |
3–0 | RESP4–RESP1 | W | 0 | Reset port bits. Used to force an immediate port(s) turn off in any mode, by writing a 1 at the corresponding RESPn bit location(s). Turning OFF a port with this command also clears the corresponding bits in Detection Event register (CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn, ILIMn), Port n Status register (CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn). Note that the port can be turned back on immediately after a port reset; this means that any ongoing cool down cycle becomes immediately terminated once a port reset is received. The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The corresponding PEn and PGn bits of Power Status Register are also updated accordingly. |