SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 0Ah with 1 Data Byte, Read only
COMMAND = 0Bh with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit D3, D2, D1, and D0 are reserved for future use.
A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read command clears all bits of the register.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSD | VDUV | VDWRN | VPUV | – | – | – | – |
R | R | R | R | R | R | R | R |
CR | CR | CR | CR | CR | CR | CR | CR |
LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset |
Bit | Field | Type | POR | Description |
---|---|---|---|---|
7 | TSD | R or CR | 0 | Indicates that a thermal shutdown occurred. When there is thermal shutdown, all ports are turned off and are put in OFF mode. The TPS2388 internal circuitry continues to operate however, including the A/D converters. Note that at as soon as the internal temperature has decreased below the low threshold, the ports can be turned back ON regardless of the status of the TSD bit. 1 = Thermal shutdown occurred 0 = No thermal shutdown occurred |
6 | VDUV | R or CR | 1 | Indicates that a VDD UVLO occurred. 1 = VDD UVLO occurred 0 = No VDD UVLO occurred |
5 | VDWRN | R or CR | 1 | Indicates that the VDD has fallen under the UVLO warning threshold. 1 = VDD UV Warning occurred 0 = No VDD UV warning occurred |
4 | VPUV | R or CR | 1 | Indicates Indicates that a VPWR undervoltage occurred. 1 = VPWR undervoltage occurred 0 = No VPWR undervoltage occurred |
Note: Pulling RESET input low will not clear VDUV or VPUV.
When VPWR undervoltage occurs, all ports are shut off if SUMSK = 1. If VPWR UVLO or VDD UVLO occurs, there is power-on reset. Note also that turning OFF a port when VPWR undervoltage occurs also clears the corresponding bits in Fault Event register (DISFn, ICUTn), Start Event register (STRTn), Port n Status register (CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn). The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The corresponding PEn and PGn bits of Power Status Register are also updated accordingly.
NOTE
A clear on Read will not effectively clear VDUV bit as long as the VPWR undervoltage condition is maintained.
NOTE
If SUMSK = 0, a VPWR undervoltage Event Fault (VPUV) will not shut off ports, as long as VPWR is above the VPWR UVLO threshold.
NOTE
During VPWR undervoltage, the Detection Event register (CLSCn, DETCn) is not cleared, unless VPWR also falls below the VPWR UVLO falling threshold.
NOTE
If VPWR UVLO or VDD UVLO occurs, the I2C interface stops operating, and SDAO is forced low.