SLUSC25 Data sheet

SLUSC25A February 2015 – August 2017 TPS2388

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTQ|56
- MPQF168D

サーマルパッド・メカニカル・データ

RTQ|56
- QFND490A

発注情報

6.6 Timing Requirements

			MIN	TYP	MAX	UNIT
f_SCL	SCL clock frequency		10		400	kHz
t_LOW	LOW period of the clock		1.3			µs
t_HIGH	HIGH period of the clock		0.6			µs
t_fo	SDAO output fall time	SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10 kΩ pull-up to 3.3 V	21		250	ns
t_fo	SDAO output fall time	SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3 kΩ pull-up to 3.3 V	21		250	ns
C_I2C	SCL capacitance				10	pF
C_{I2C_SDA}	SDAI, SDAO capacitance (each)				6	pF
t_SU,DATW	Data set-up time (Write operation)		100			ns
t_SU,DATR	Data set-up time (Read operation)	SDAO, Cb = 10 pF, 1.3 kΩ pull-up to 3.3V	600			ns
t_HD,DATW	Data hold time (Write operation)		0			ns
t_HD,DATR	Data hold time (Read operation)		150		600	ns
t_fSDA	Input fall times of SDAI	2.3 → 0.8 V	20		250	ns
t_rSDA	Input rise times of SDAI	0.8 → 2.3 V	20		300	ns
t_r	Input rise time of SCL	0.8 → 2.3 V	20		300	ns
t_f	Input fall time of SCL	2.3 → 0.8 V	20		200	ns
t_BUF	Bus free time between a STOP and START condition		1.3			µs
t_HD,STA	Hold time after (repeated) Start condition		0.6			µs
t_SU,STA	Repeated Start condition set-up time		0.6			µs
t_SU,STO	Stop condition set-up time		0.6			µs
t_{FLT_INT}	Fault to INT assertion	Time to internally register an Interrupt fault, from port turn off		50	500	µs
t_DG	Suppressed spike pulse width, SDAI and SCL		50			ns
t_RDG	RESET input minimum pulse width (deglitch time)				5	µs
t_{bit_OSS}	3-bit OSS bit period	MbitPrty = 1	24	25	26	µs
t_{OSS_IDL}	Idle time between consecutive shutdown code transmission in 3-bit mode	MbitPrty = 1	48	50		µs
t_{r_OSS}	Input rise time of OSS in 3-bit mode	0.8 → 2.3 V, MbitPrty = 1	1		300	ns
t_{f_OSS}	Input fall time of OSS in 3-bit mode	2.3 → 0.8 V, MbitPrty = 1	1		300	ns
t_{WDT_I2C}	I²C Watchdog trip delay		1.1	2.2	3.3	s