JAJSHY0D August 2019 – August 2020 TPS23882
PRODUCTION DATA
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 I2C Programming
- 9.6
Register Maps
- 9.6.1 Complete Register Set
- 9.6.2
Detailed Register Descriptions
- 9.6.2.1 INTERRUPT Register
- 9.6.2.2 INTERRUPT MASK Register
- 9.6.2.3 POWER EVENT Register
- 9.6.2.4 DETECTION EVENT Register
- 9.6.2.5 FAULT EVENT Register
- 9.6.2.6 START/ILIM EVENT Register
- 9.6.2.7 SUPPLY and FAULT EVENT Register
- 9.6.2.8 CHANNEL 1 DISCOVERY Register
- 9.6.2.9 CHANNEL 2 DISCOVERY Register
- 9.6.2.10 CHANNEL 3 DISCOVERY Register
- 9.6.2.11 CHANNEL 4 DISCOVERY Register
- 9.6.2.12 POWER STATUS Register
- 9.6.2.13 PIN STATUS Register
- 9.6.2.14 OPERATING MODE Register
- 9.6.2.15 DISCONNECT ENABLE Register
- 9.6.2.16 DETECT/CLASS ENABLE Register
- 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
- 9.6.2.18 TIMING CONFIGURATION Register
- 9.6.2.19 GENERAL MASK Register
- 9.6.2.20 DETECT/CLASS RESTART Register
- 9.6.2.21 POWER ENABLE Register
- 9.6.2.22 RESET Register
- 9.6.2.23 ID Register
- 9.6.2.24 Connection Check and Auto Class Status Register
- 9.6.2.25 2-Pair Police Ch-1 Configuration Register
- 9.6.2.26 2-Pair Police Ch-2 Configuration Register
- 9.6.2.27 2-Pair Police Ch-3 Configuration Register
- 9.6.2.28 2-Pair Police Ch-4 Configuration Register
- 9.6.2.29 Capacitance (Legacy PD) Detection
- 9.6.2.30 Power-on Fault Register
- 9.6.2.31 PORT RE-MAPPING Register
- 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
- 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
- 9.6.2.34 Port Power Allocation Register
- 9.6.2.35 TEMPERATURE Register
- 9.6.2.36 INPUT VOLTAGE Register
- 9.6.2.37 CHANNEL 1 CURRENT Register
- 9.6.2.38 CHANNEL 2 CURRENT Register
- 9.6.2.39 CHANNEL 3 CURRENT Register
- 9.6.2.40 CHANNEL 4 CURRENT Register
- 9.6.2.41 CHANNEL 1 VOLTAGE Register
- 9.6.2.42 CHANNEL 2 VOLTAGE Register
- 9.6.2.43 CHANNEL 3 VOLTAGE Register
- 9.6.2.44 CHANNEL 4 VOLTAGE Register
- 9.6.2.45 2x FOLDBACK SELECTION Register
- 94
- 9.6.2.46 FIRMWARE REVISION Register
- 9.6.2.47 I2C WATCHDOG Register
- 9.6.2.48 DEVICE ID Register
- 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
- 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
- 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
- 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
- 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
- 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
- 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
- 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
- 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
- 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
- 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
- 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
- 9.6.2.61 AUTO CLASS CONTROL Register
- 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
- 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
- 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
- 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
- 9.6.2.66 ALTERNATIVE FOLDBACK Register
- 9.6.2.67 SRAM CONTROL Register
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
- RTQ|56
サーマルパッド・メカニカル・データ
- RTQ|56
発注情報
7.6 Typical Characteristics
Conditions are –40 < TJ < 125 °C unless otherwise noted.VVDD = 3.3 V, VVPWR = 54 V, VDGND = VAGND, DGND, KSENSA, KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into pins. RS = 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating registers loaded with default values unless otherwise noted.
Figure 7-1 VPWR
Current Consumption vs Temperature
Figure 7-3 VPUV
Thresholds vs Temperature
Figure 7-5 VDUV
Thresholds vs Temperature
Figure 7-7 Discovery Currents vs Temperature
Figure 7-9 Discovery Open Circuit Voltage vs Temperature
Figure 7-11 Mark Voltage vs IMARK and Temperature
Figure 7-13 Power Good Threshold vs Temperature
Figure 7-15 Port Voltage ADC Measurement vs Temperature
Figure 7-17 Port Current ADC Measurement (100mA) vs Temperature
Figure 7-19 Port Current ADC Measurement (1 A) vs Temperature
Figure 7-21 Inrush Current Limit vs Temperature
Figure 7-23 2x Mode (2xFBn = 1) Current Limit vs Temperature
Figure 7-25 ROFF (VPWR to DRAIN) vs Temperature
Figure 7-27 1x Mode (2xFBn = 0) Current Foldback vs Drain Voltage
Figure 7-2 VPWR
UVLO Thresholds vs Temperature
Figure 7-4 VDD
Current Consumption vs Temperature
Figure 7-6 SENSE
Pin Bias Current vs Temperature
Figure 7-8 Discovery Resistance Measurement vs Temperature
Figure 7-10 Classification Voltage vs ICLASS and Temperature
Figure 7-12 Classification and Mark Current Limit vs Temperature
Figure 7-14 Gate Voltage (Port On) vs Temperature
Figure 7-16 VPWR Voltage ADC Measurement vs Temperature
Figure 7-18 Port Current ADC Measurement (770mA) vs Temperature
Figure 7-20 PCut Threshold (30W) vs Temperature
Figure 7-22 1x Mode (2xFBn = 0) Current Limit vs Temperature
Figure 7-24 ISHORT Threshold vs Temperature
Figure 7-26 Inrush Current Foldback vs Port Voltage
Figure 7-28 2x Mode (2xFBn = 1) Current Foldback vs Drain Voltage