JAJS177F November   2003  – February 2020 TPS2490 , TPS2491

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC
      2. 7.3.2  SENSE
      3. 7.3.3  GATE
      4. 7.3.4  OUT
      5. 7.3.5  EN
      6. 7.3.6  VREF
      7. 7.3.7  PROG
      8. 7.3.8  TIMER
      9. 7.3.9  PG
      10. 7.3.10 GND
    4. 7.4 Device Functional Modes
      1. 7.4.1 Board Plug-In ()
      2. 7.4.2 TIMER and PG Operation ()
      3. 7.4.3 Action of the Constant Power Engine ()
      4. 7.4.4 Response to a Hard Output Short ( and )
      5. 7.4.5 Automatic Restart ()
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Alternative Inrush Designs
        1. 8.1.1.1 Gate Capacitor (dV/dt) Control
        2. 8.1.1.2 PROG Inrush Control
      2. 8.1.2 Additional Design Considerations
        1. 8.1.2.1 Use of PG
        2. 8.1.2.2 Faults and Backplane Voltage Droop
        3. 8.1.2.3 Output Clamp Diode
        4. 8.1.2.4 Gate Clamp Diode
        5. 8.1.2.5 High Gate Capacitance Applications
        6. 8.1.2.6 Input Bypass
        7. 8.1.2.7 Output Short Circuit Measurements
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select RSNS and CL setting
        2. 8.2.2.2 Selecting the Hot Swap FET(s)
        3. 8.2.2.3 Select Power Limit
        4. 8.2.2.4 Set Fault Timer
        5. 8.2.2.5 Check MOSFET SOA
        6. 8.2.2.6 Set Under-Voltage Threshold
        7. 8.2.2.7 Choose R5, and CIN
        8. 8.2.2.8 Input and Output Protection
        9. 8.2.2.9 Final Schematic and Component Values
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGS|10
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and all outputs unloaded; positive currents are into pins.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (VCC)
Enabled VEN = Hi, VSENSE = VOUT = VVCC 450 1000 µA
Disabled VEN = Lo, VSENSE = VVCC = VOUT 90 250 µA
CURRENT SENSE INPUT (SENSE)
ISENSE Input bias current VSENSE = VVCC, VOUT = VVCC 7.5 20 µA
REFERENCE VOLTAGE OUTPUT (VREF)
VREF Reference voltage 0 < IVREF < 1 mA 3.9 4 4.1 V
POWER LIMITING INPUT (PROG)
IPROG Input bias current, device enabled, sourcing or sinking 0 < VPROG < 4 V, VEN = 48 V 5 µA
RPROG Pulldown resistance, device disabled IPROG = 200 µA, VEN = 0 V 375 600 Ω
POWER LIMITING AND CURRENT LIMITING (SENSE)
VCL Current sense threshold V(VCC-SENSE) with power limiting trip VPROG = 2.4 V, VOUT = 0 V or
VPROG = 0.9 V, VOUT = 30 V, VVCC = 48 V		 17 25 33 mV
VSENSE Current sense threshold V(VCC-SENSE) without power limiting trip VPROG = 4 V, VSENSE = VOUT 45 50 55 mV
TIMER OPERATION (TIMER)
Charge current (sourcing) VTIMER = 0 V 15 25 34 µA
VTIMER = 0 V, TJ = 25°C 20 25 30 µA
Discharge current (sinking) VTIMER = 5 V 1.5 2.5 3.7 µA
VTIMER = 5 V, TJ = 25°C 2.1 2.5 3.1 µA
TIMER upper threshold voltage 3.9 4 4.1 V
TIMER lower reset threshold voltage TPS2491 only 0.96 1 1.04 V
DRETRY Fault retry duty cycle TPS2491 only 0.5% 0.75% 1%
GATE DRIVE OUTPUT (GATE)
IGATE GATE sourcing current VSENSE = VVCC, V(GATE-OUT) = 7 V,
VEN = Hi		 15 22 35 µA
GATE sinking current VEN = Lo, VGATE = VVCC 1.8 2.4 2.8 mA
VEN = Hi, VGATE = VVCC,
V(VCC-SENSE) ≥ 200 mV		 75 125 250 mA
GATE output voltage, V(GATE-OUT) 12 16 V
POWER GOOD OUTPUT (PG)
VPG_L Low voltage (sinking) IPG = 2 mA 0.1 0.25 V
IPG = 4 mA 0.25 0.5 V
VPGTL PG threshold voltage, VOUT rising, PG goes open drain VSENSE = VVCC, measure V(VCC-OUT) 0.8 1.25 1.7 V
VPGTH PG threshold voltage, VOUT falling, PG goes low VSENSE = VVCC, measure V(VCC-OUT) 2.2 2.7 3.2 V
ΔVPGT PG threshold hysteresis voltage, V(SENSE-OUT) VSENSE = VVCC 1.4 V
Leakage current, PG false, open drain 10 µA
OUTPUT VOLTAGE FEEDBACK INPUT (OUT)
IOUT Bias current VOUT = VVCC, VEN = Hi, sinking 8 20 µA
VOUT = GND, VEN = Lo, sourcing 18 40 µA
ENABLE INPUT (EN)
VEN_H Threshold, VEN going high 1.32 1.35 1.38 V
VEN_L Threshold, VEN going low 1.22 1.25 1.28 V
VEN hysteresis 100 mV
Leakage current VEN = 48 V 1 µA
INPUT SUPPLY UVLO (VCC)
VVCC turn on Rising 8.4 8.8 V
VVCC turn off Falling 7.5 8.3 V
Hysteresis 75 mV