SLVSDG8B April   2016  – June 2017 TPS25740 , TPS25740A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  USB PD BMC Transmission (CC1, CC2, VTX)
      3. 8.3.3  USB PD BMC Reception (CC1, CC2)
      4. 8.3.4  Discharging (DSCG, VPWR)
        1. 8.3.4.1 Discharging after a Fault (VPWR)
      5. 8.3.5  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      6. 8.3.6  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      7. 8.3.7  Gate Driver (GDNG, GDNS)
      8. 8.3.8  Fault Monitoring and Protection
        1. 8.3.8.1 Over/Under Voltage (VBUS)
        2. 8.3.8.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.8.3 System Fault Input (GD, VPWR)
      9. 8.3.9  Voltage Control (CTL1, CTL2)
      10. 8.3.10 Sink Attachment Indicator (UFP, DVDD)
      11. 8.3.11 Power Supplies (VAUX, VDD, VPWR, DVDD)
      12. 8.3.12 Grounds (AGND, GND)
      13. 8.3.13 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (R(FBL1) and R(FBL2))
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG C(SLEW)
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Application , A/C Power Source (Wall Adapter)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Non-Configurable Components
        3. 9.2.2.3 Configurable Components
      3. 9.2.3 Application Curves
      4. 9.2.4 Typical Application, D/C Power Source
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Power Pin Bypass Capacitors
          2. 9.2.4.2.2 Non-Configurable Components
          3. 9.2.4.2.3 Configurable Components
        3. 9.2.4.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 D/C Power Source (Power Hub)
      2. 9.3.2 A/C Power Source (Wall Adapter)
      3. 9.3.3 Dual-Port Power Managed A/C Power Source (Wall Adaptor)
      4. 9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Port Current Kelvin Sensing
    2. 11.2 Layout Guidelines
      1. 11.2.1 Power Pin Bypass Capacitors
      2. 11.2.2 Supporting Components
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.