JAJSRT8A
October 2023 – March 2024
TPS25751
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.1.1
TPS25751D and TPS25751S - Absolute Maximum Ratings
6.1.2
TPS25751D - Absolute Maximum Ratings
6.1.3
TPS25751S - Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.3.1
TPS25751D - Recommended Operating Conditions
6.3.2
TPS25751S - Recommended Operating Conditions
6.4
Recommended Capacitance
6.5
Thermal Information
6.5.1
TPS25751D - Thermal Information
6.5.2
TPS25751S - Thermal Information
6.6
Power Supply Characteristics
6.7
Power Consumption
6.8
PP_5V Power Switch Characteristics
6.9
PPHV Power Switch Characteristics - TPS25751D
6.10
PP_EXT Power Switch Characteristics - TPS25751S
6.11
Power Path Supervisory
6.12
CC Cable Detection Parameters
6.13
CC VCONN Parameters
6.14
CC PHY Parameters
6.15
Thermal Shutdown Characteristics
6.16
ADC Characteristics
6.17
Input/Output (I/O) Characteristics
6.18
BC1.2 Characteristics
6.19
I2C Requirements and Characteristics
6.20
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
USB-PD Physical Layer
8.3.1.1
USB-PD Encoding and Signaling
8.3.1.2
USB-PD Bi-Phase Marked Coding
8.3.1.3
USB-PD Transmit (TX) and Receive (Rx) Masks
8.3.1.4
USB-PD BMC Transmitter
8.3.1.5
USB-PD BMC Receiver
8.3.1.6
Squelch Receiver
8.3.2
Power Management
8.3.2.1
Power-On And Supervisory Functions
8.3.2.2
VBUS LDO
8.3.3
Power Paths
8.3.3.1
Internal Sourcing Power Paths
8.3.3.1.1
PP_5V Current Clamping
8.3.3.1.2
PP_5V Local Overtemperature Shut Down (OTSD)
8.3.3.1.3
PP_5V OVP
8.3.3.1.4
PP_5V UVLO
8.3.3.1.5
PP_5Vx Reverse Current Protection
8.3.3.1.6
PP_CABLE Current Clamp
8.3.3.1.7
PP_CABLE Local Overtemperature Shut Down (OTSD)
8.3.3.1.8
PP_CABLE UVLO
8.3.3.2
TPS25751D Internal Sink Path
8.3.3.2.1
Overvoltage Protection (OVP)
8.3.3.2.2
Reverse-Current Protection (RCP)
8.3.3.2.3
VBUS UVLO
8.3.3.2.4
Discharging VBUS to Safe Voltage
8.3.3.3
TPS25751S - External Sink Path Control PP_EXT
8.3.3.3.1
Overvoltage Protection (OVP)
8.3.3.3.1.1
Reverse-Current Protection (RCP)
8.3.3.3.1.2
VBUS UVLO
8.3.3.3.1.3
Discharging VBUS to Safe Voltage
8.3.4
Cable Plug and Orientation Detection
8.3.4.1
Configured as a Source
8.3.4.2
Configured as a Sink
8.3.4.3
Configured as a DRP
8.3.4.4
Dead Battery Advertisement
8.3.5
Overvoltage Protection (CC1, CC2)
8.3.6
Default Behavior Configuration (ADCIN1, ADCIN2)
8.3.7
ADC
8.3.8
BC 1.2 (USB_P, USB_N)
8.3.9
Digital Interfaces
8.3.9.1
General GPIO
8.3.9.2
I2C Interface
8.3.10
Digital Core
8.3.11
I2C Interface
8.3.11.1
I2C Interface Description
8.3.11.1.1
I2C Clock Stretching
8.3.11.1.2
I2C Address Setting
8.3.11.1.3
Unique Address Interface
8.4
Device Functional Modes
8.4.1
Pin Strapping to Configure Default Behavior
8.4.2
Power States
8.5
Thermal Shutdown
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Programmable Power Supply (PPS) - Design Requirements
9.2.1.2
Liquid Detection Design Requirements
9.2.1.3
BC1.2 Application Design Requirements
9.2.1.4
USB Data Support Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Programmable Power Supply (PPS)
9.2.2.2
Liquid Detection
9.2.2.2.1
Liquid Detection Operation
9.2.2.3
BC1.2 Application
9.2.2.4
USB Data Support
9.2.3
Application Curves
9.2.3.1
Programmable Power Supply (PPS) Application Curves
9.2.3.2
Liquid Detection Application Curves
9.2.3.3
BC1.2 Application Curves
9.2.3.4
USB Data Support Application Curves
9.3
Power Supply Recommendations
9.3.1
3.3-V Power
9.3.1.1
VIN_3V3 Input Switch
9.3.2
1.5-V Power
9.3.3
Recommended Supply Load Capacitance
9.4
Layout
9.4.1
TPS25751D - Layout
9.4.1.1
Layout Guidelines
9.4.1.1.1
Recommended Via Size
9.4.1.1.2
Minimum Trace Widths
9.4.1.2
Layout Example
9.4.1.2.1
TPS25751D Schematic Layout Example
9.4.1.2.2
TPS25751D Layout Example - PCB Plots
9.4.1.2.2.1
TPS25751D Component Placement
9.4.1.2.2.2
TPS25751D PP5V
9.4.1.2.2.3
TPS25751D PPHV
9.4.1.2.2.4
TPS25751D VBUS
9.4.1.2.2.5
TPS25751D I/O (I2C, ADCINs, GPIOs)
9.4.1.2.2.6
TPS25751D DRAIN
9.4.1.2.2.7
TPS25751D GND
9.4.2
TPS25751S - Layout
9.4.2.1
Layout Guidelines
9.4.2.1.1
Recommended Via Size
9.4.2.1.2
Minimum Trace Widths
9.4.2.2
Layout Example
9.4.2.2.1
TPS25751S Schematic Layout Example
9.4.2.2.2
TPS25751S Layout Example - PCB Plots
9.4.2.2.2.1
TPS25751S Component Placement
9.4.2.2.2.2
TPS25751S PP5V
9.4.2.2.2.3
TPS25751S PP_EXT
9.4.2.2.2.4
TPS25751S VBUS
9.4.2.2.2.5
TPS25751S I/O
9.4.2.2.2.6
TPS25751S PPEXT Gate Driver
9.4.2.2.2.7
TPS25751S GND
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.1.2
Firmware Warranty Disclaimer
10.2
Documentation Support
10.2.1
Related Documentation
10.3
ドキュメントの更新通知を受け取る方法
10.4
サポート・リソース
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
REF|38
MPQF652A
RSM|32
MPQF195B
サーマルパッド・メカニカル・データ
RSM|32
QFND112H
発注情報
jajsrt8a_oa
jajsrt8a_pm
9.2.2
Detailed Design Procedure