Data Sheet
TPS25762-Q1 車載用 USB Type-C® パワー デリバリ コントローラ、昇降圧レギュレータ
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1 特長
- 以下の結果で AEC-Q100 認定済み：
- デバイス温度グレード 1：動作時周囲温度範囲 -40℃～+125℃
- デバイス HBM ESD 分類レベル 2
- デバイス CDM ESD 分類レベル C2b
- 拡張コネクタ ピン ESD 保護
- プログラマブル電源 (PPS) サポート付き USB パワー デリバリ (PD) コントローラ
- 広い VIN：5.5V～18V (最大 40V)
- 4 個のパワー スイッチを搭載し、最大 65W の USB PD 出力電力をサポートする統合型昇降圧
- VBUS 出力：3.3～21V、±20mV のステップ サイズ
- IBUS 出力：0～3A、±50mA の電流制限ステップ サイズ
- VBUS から VBAT および GND への短絡保護
- VBUS ケーブル ドループ補償
- MFI 過電流保護
- スイッチング周波数：300、400、450kHz
- ディザリングによる DC/DC 同期入出力
- USB ポート構成オプション
- 1 つの USB-PD ポート (TPS25762-Q1)
- USB-C™ 経由の DisplayPort™ (DP 代替モード) を備えた 1 つの USB-PD ポート (TPS25763-Q1)
- 2 つの USB-PD ポート (TPS25772-Q1)
- USB 準拠
- USB Type-C® パワー デリバリ リビジョン 3.1
- TPS25762-Q1：PPS、TID による USB–IF 認定：9509
- TPS25772-Q1：PPS、TID による USB–IF 認定：9161
- CC ロジック、VCONN ソースおよび放電
- USB ケーブルの極性検出
- バッテリ充電仕様バージョン 1.2 (BC1.2)
- DCP：専用充電ポート
- USB Type-C® パワー デリバリ リビジョン 3.1
- 従来型高速充電
- 2.7V 分圧回路 3 モード
- 1.2V 分圧回路モード
- 高電圧 DCP プロトコル
- マイコン コア
- ファームウェア更新
- 電源電圧と温度によって動作が異なるパワー マネージメント
- VBUS および VBAT への短絡保護
- VBUS
- Px_DP および Px_DM
- Px_CC1、Px_CC2
- ウェッタブル フランク付きの HotRod™ QFN パッケージ
2 アプリケーション
3 概要
TPS25762-Q1 は、車載用シングル USB ポート アプリケーション向けの昇降圧コンバータを内蔵した統合型 USB Type-C® パワー デリバリ (PD) ソリューションです。4 つのパワー スイッチを備えた統合型昇降圧コンバータ、ARM® Cortex®-M0、Type-C ケーブル プラグおよび方向検出機能を備えた USB ポート コントローラ、USB バッテリ充電仕様バージョン 1.2 (BC1.2) 検出、USB エンドポイント PHY、デバイスの電源管理および監視回路、コネクタ ピンの過電圧および短絡保護の機能が搭載されています。
インテリジェントなシステム パワー マネジメント (SPM) エンジンは、供給される USB 電力を最大化すると同時に、車載用バッテリの過渡状態や過熱状態からシステムを保護します。
デバイス構成設定は、直感的なグラフィカル ユーザー インターフェイス (GUI) を使用して選択できます。
(1) 詳細については、Mechanical, Packaging, and Orderable Information を参照してください。
(2) パッケージ サイズ
(長さ × 幅) は公称値であり、該当する場合はピンも含まれます。
TPS25762-Q1 の概略回路図4 Device Comparison Table
| PART NUMBER | Orderable Device | Port A | Port B | Port A Output Power | Port B Output Power | DP Alternate Mode | Astable VIN Boot Support | Configurable Boot Mode(2) |
|---|---|---|---|---|---|---|---|---|
| TPS25762-Q1 | TPS25762CQRQLRQ1 | USB-PD | n/a | 65 W | n/a | No | VIN-dependent(1) | Yes |
| TPS25762CAQRQLRQ1 | Yes | No | ||||||
| TPS25762DQRQLRQ1 | Yes | Yes | ||||||
| TPS25772-Q1 | TPS25772CQRQLRQ1 | USB-PD | 65 W | No | VIN-dependent(1) | Yes | ||
| TPS25772CAQRQLRQ1 | Yes | No | ||||||
| TPS25772DQRQLRQ1 | Yes | Yes | ||||||
| TPS25763-Q1 | TPS25763DQRQLRQ1 | n/a | n/a | Yes | Yes | Yes |
- Assured device boot up during a stable VIN (for example, cold crank) conditions when VIN oscillation minimum voltage is ≧7.6V until boot is completed. Refer to application brief TPS257x2-Q1 Startup with an Astable Supply Voltage.
- Refer to Section 8.3.2.
5 Pin Configuration and Functions
Figure 5-1 RQL Package29-Pin (VQFN)Top ViewTable 5-1 Pin Descriptions
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NAME | NO. | ||
| EN/UVLO | 6 | Enable pin. For EN/UVLO < 0.3 V, the TPS25762-Q1 is in a low current shutdown mode. For EN/UVLO > 1.3 V, the full functionality is enabled, provided LDO_5V exceeds the LDO_5V UVLO threshold. | |
| IN | 15 | The input supply pin to the IC. Connect VIN to a supply voltage between 5.5 V and 18 V (40-V ABS MAX transient). | |
| PGND | 13 | Power ground of the IC. The high current ground connection to the low-side gate drivers. | |
| SW1 | 14 | The buck side switching node. | |
| SW2 | 12 | The boost side switching node. | |
| BOOT1 | 16 | An external capacitor is required between the BOOT1 and the SW1 pins to provide bias to the high-side MOSFET gate drivers. | |
| BOOT2 | 10 | An external capacitor is required between the BOOT2 and the SW2 pins to provide bias to the high-side MOSFET gate drivers. | |
| AGND | 5 | Analog ground of the IC. | |
| OUT | 11 | Output of the buck-boost regulator. Connect to bulk capacitance. | |
| CSP | 28 | Positive input of the current sense amplifier. | |
| CSN/BUS | 29 | Negative input of the current sense amplifier. This is the PA_VBUS supply. | |
| LDO_5V | 21 | Output of internal 5 V LDO for buck-boost low-side FET drivers, and Px_VCONN supply. Connect bypass capacitor to PGND. May be overdriven from external 5-V supply. | |
| LDO_3V3 | 27 | Output of internal 3.3-V LDO for analog circuitry and GPIO drivers. Connect bypass capacitor to AGND. | |
| LDO_1V5 | 7 | Output of internal 1.5-V LDO for digital circuitry. Connect bypass capacitor to AGND. | |
| I2C_SCL1 | 3 | Controller I2C Clock Input/Output. | |
| I2C_SDA1 | 4 | Controller I2C Data Input/Output. | |
| GPIO2 (I2C_SCL2) | 25 | Multifunction pin. GPIO; or target I2C Clock Input. | |
| GPIO3 (I2C_SDA2) | 26 | Multifunction pin. GPIO; or target I2C Data Input. | |
| IRQ (GPIO9) | 2 | Multifunction pin. Interrupt I/O and fault flag for I2C1 or I2C2; or GPIO depending upon firmware configuration. Reports fault conditions set by application configuration firmware. | |
| PA_CC1 | 20 | Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC1 pin. | |
| PA_CC2 | 19 | Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC2 pin. | |
| PA_DP (GPIO8) | 18 | Multifunction pin. BC1.2 USB 2.0 D+ data line input/output. Connect to Port A Type-C USB data line DP connector pins. May also be used as GPIO depending upon firmware configuration. | |
| PA_DM (GPIO7) | 17 | Multifunction pin. BC1.2 USB 2.0 D- data line input/output. Connect to Port A Type-C USB data line DM connector pins. May also be used as GPIO depending upon firmware configuration. | |
| GPIO0 | 23 | GPIO | |
| GPIO1 or IRQ2(o) | 24 | Multifunction pin. GPIO or Interrupt I/O depending upon firmware configuration. | |
| GPIO5 (NTC) | 8 | Multifunction pin. GPIO; thermistor input (can use either negative temperature coefficient resistor or positive temperature coefficient resistor). | |
| GPIO6 (SYNC) | 1 | Multifunction pin. GPIO; SYNC(o) - clock out to synchronize external DC/DC regulators to internal DC/DC switching frequency; SYNC(i) - clock input to synchronize internal DC/DC to an external clock. | |
| PA_LSGD | 9 | Charge pump output for external NFET for VBUS bulk capacitance blocking. | |
| TVSP | 22 | Transient voltage protection and firmware setting pin. See TVSP Device Configuration and ESD Protection for boot configuration and R-C network component values. | |
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise noted)(1)(2)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input voltage range | IN (3)(4) to PGND | –0.3 | 40 | V |
| Input voltage range | IN with respect to SW1 | –0.3 | 25 | V |
| Input voltage range | EN/UVLO (5) to AGND | –0.3 | internally limited | V |
| Input voltage range | BOOT1 with respect to SW1 | –0.3 | 6 | V |
| Input voltage range | BOOT2 with respect to SW2 (6) | –0.3 | 6 | V |
| Input voltage range | SW1 (7) to PGND | –0.3 | 24 | V |
| Input voltage range | SW2 (8) to PGND | –0.3 | 24 | V |
| Input voltage range | SW2 to OUT | 17.5 | V | |
| Input voltage range | CSP to PGND | –0.3 | 24 | V |
| Input voltage range | CSN/BUS to PGND | –0.3 | 24 | V |
| Input voltage range | CSP to CSN | -0.3 | 0.3 | V |
| Input voltage range | AGND to PGND | –0.3 | 0.3 | V |
| Output voltage range | OUT to PGND | –0.3 | 24 | V |
| Output voltage range | LDO_5V to PGND | –0.3 | 6 | V |
| Output voltage range | LDO_3V3 to AGND | –0.3 | 6 | V |
| Output voltage range | LDO_1V5 to AGND | –0.3 | 2 | V |
| I/O voltage range | TVSP to PGND | –0.3 | 30 | V |
| I/O voltage range | I2C_SCL1 to AGND | –0.3 | 6 | V |
| I/O voltage range | I2C_SDA1 to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO9, IRQ1 to AGND | –0.3 | 6 | V |
| I/O voltage range | PA_CC1 to AGND | –0.3 | 30 | V |
| I/O voltage range | PA_CC2 to AGND | –0.3 | 30 | V |
| I/O voltage range | PA_DM to AGND | –0.3 | 30 | V |
| I/O voltage range | GPIO7 to AGND | –0.3 | 6 | V |
| I/O voltage range | PA_DP to AGND | –0.3 | 30 | V |
| I/O voltage range | GPIO8 to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO0 to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO1, IRQ2 to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO2, I2C_SCL2 to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO3, I2C_SDA2 to AGND | –0.3 | 6 | V |
| I/O voltage range | PA_LSGD to PGND | –0.3 | 30 | V |
| I/O voltage range | GPIO5, NTC to AGND | –0.3 | 6 | V |
| I/O voltage range | GPIO6, SYNC to AGND | –0.3 | 6 | V |
| I/O voltage range | PA_LSGD to CSN/BUS | –0.3 | 10 | V |
| Input current | EN/UVLO | 0 | 2 | mA |
| Output current | Positive source current on PA_CC1, PA_CC2 | internally limited | A | |
| Output current | GPIO 2, 3, 5, 6, 7, 8 | 0.0010 | A | |
| Output current | GPIO 0, 1, 4, 9 | 0.005 | A | |
| Output current | positive sink current for I2C_SDA1, I2C_SCL1, I2C_SDA2, I2C2_SCL2 | internally limited | A | |
| Output current | positive source current for LDO_5V, LDO_3V3, LDO_1V5 | internally limited | A | |
| TA Operating ambient temperature | –40 | 125 | °C | |
| TJ Operating junction temperature | –40 | 150 | °C | |
| TSTG Storage temperature | –55 | 150 | °C | |
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to PGND or AGND. Connect the PGND pin directly to the Ground plane of the board. The PGND and AGND traces can be connected near the AGND pin.
(3) When the buck-boost is operating and VIN exceeds 18 V, the positive slew rate dVIN/dt must not exceed 200V/ms.
(4) When applying VIN, the time from VIN exceeding 5 V to VIN exceeding 25 V must not be less than 2 µs and can be achieved by properly sizing the input EMI filter.
(5) EN/UVLO pin is internally clamped to 10V. Ensure input current rating is not exceeded by connecting current limit resistor.
(6) BOOT2 with respect to SW2 during OUT overvoltage conditions can be -15 V due to internal clamp.
(7) SW1 can undershoot PGND by -1 V during negative switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW1 can overshoot OUT by 1 V during positive transients. Typical duration ~ 20 ns.
(8) SW2 can undershoot PGND by -2 V during switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW2 can overshoot OUT by 1 V during positive transients. Typical duration ~20 ns.
6.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002 | ±2000(1) | V | |
| V(ESD) | Electrostatic discharge | Charged-device model (CDM), per AEC Q100-011 | ±750(2) | V | |
| V(ESD) | Electrostatic discharge | IEC61000-4-2 Contact discharge 150 pF, 330 Ω. | OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM | ±2000(3) | V |
| V(ESD) | Electrostatic discharge | IEC61000-4-2 Contact discharge 150 pF, 330 Ω. | OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM | ±2000(3) | V |
| V(ESD) | Electrostatic discharge | ISO 10605 Contact discharge 330 pF, 330 Ω. | OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM | ±2000(3) | V |
| V(ESD) | Electrostatic discharge | ISO 10605 Air-gap discharge 330 pF, 330 Ω. | OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM | ±2000(3) | V |
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification C2b.
(3) Test conducted on Texas Instruments evaluation board.
