The TPS25763-Q1 is a fully-integrated AEC-Q100 USB Power Delivery (USB-PD) source intended for use in 12-V automotive battery systems. Input supply pin, V_IN, must be connected to a load dump clamped battery supply, V_BAT, and never exceed 40 V (ABS MAX).

The device consists of seven sub-blocks: USB-PD controller; Type-C cable plug and orientation detection circuitry; USB Endpoint; USB Battery Charging Specification Version 1.2 (BC1.2) detection circuitry; digital core; device power management and supervisory circuitry; and a buck-boost converter with 4 integrated power switches.

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, see USB-PD Physical Layer.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, see Cable Plug and Orientation Detection.

A USB Endpoint is included for downloading configuration information and firmware updates. On the TPS25763-Q1, the USB Endpoint provides billboard functionality in the event of an Alternate Mode error. When enabled by firmware, the USB Endpoint connects to the PA_DP and PA_DM pins.

The USB BC1.2 sub-block contains circuitry to support legacy USB charging methods which signal on the USB DP and DM data lines including: DCP, Divider-3, 1.2 V mode, HVDCP. For additional detail, see BC 1.2, legacy and fast charging modes (Px_DP, Px_DM).

The power management and supervisory circuitry generates the LDO_5V, LDO_3V3, and LDO_1V5 voltage rails used by the device. LDO_5V supplies the LDO_3V3 and LDO_1V5 rails. For a high-level block diagram of the power management circuitry, a description of its features and more detailed operation, see Internal LDO Regulators section.

The digital core contains an ARM Cortex-M0 with 160-kB ROM and 27-kB RAM memory. The ROM contains firmware code to execute device functionality. RAM stores application configuration code created using a Graphical User Interface (GUI) and post-manufacturing firmware updates. The digital core is the engine for autonomously managing the system including: USB port connection status and communication; system power budget and allocation; system thermal monitoring and load shedding; and fault detection and reporting. All devices contain one controller I²C port (I²C1) for controlling external peripherals such as external EEPROM memory; DC/DC converters; USB data multiplexers/redrivers; GPIO expanders; and additional temperature sensors. Some devices include an I²C target port (I²C2) for connection to an external processor, HUB or embedded controller. An integrated 8-bit analog-to-digital converter ADC (see the ADC section) monitors USB port telemetry information. USB port connection status, voltage, current and fault information can be read from I²C2 target port. For a high-level block diagram of the digital core and a description of its features, see the Digital Core section.

The integrated buck-boost DC/DC converter supplies the PA_VBUS power source. The integrated DC/DC operates in buck mode when V_IN is greater than V_OUT and boost mode when V_IN is less than V_OUT. When V_IN and V_OUT are nearly the same, it operates in transition mode.

Single Port Device

TPS25763-Q1 is a single USB-PD port device. Refer to Device Comparison Table for dual port options. The TPS25763-Q1 device consists of a single 3.3 to 21 V output internal buck-boost converter, one USB-PD port controller providing cable plug and orientation detection, one internal VCONN source path, legacy USB Battery Charging Specification v1.2 Dedicated Charging Port (DCP) as well as legacy (non-USB compliant) charger detection including: Divider-3, 1.2 V, and HVDCP modes. The TPS25763-Q1 device communicates with its connected USB Type-C cable and downstream USB device at the opposite end of the cable to determine connection state and enables VBUS sourcing as appropriate.