JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Buck-Boost Regulator Operation

The TPS25772-Q1 devices utilize a fixed frequency, current mode control buck-boost converter. This converter operates in forced continuous conduction mode (CCM) and therefore allows inductor current to flow in either direction at light loads. The power train consists of five N-Channel power MOSFETs. See Figure 9-7. Transistors M1 and M2 are the high-side and low-side buck FETs. Transistors M3 and M4 are the high-side and low-side boost FETs. Transistor M5 blocks reverse conduction from OUT to SW2 during input overvoltage transients as explained in VIN Supply and VIN Over-Voltage Protection.

  • IN: Receives power from the battery. The input bulk capacitor must be connected between IN and PGND.
  • OUT: Delivers power from the switching converter. The output bulk capacitor connects between OUT to PGND.
  • PGND: Ground return for the switching converter power train.
  • AGND: Ground return for everything except the power train. The voltage feedback divider returns to AGND. PGND and AGND must connect together on the circuit board.
  • LDO_5V: Provides gate drive for M2 and M4 and current for the bootstrap circuits feeding BOOT1 and BOOT2. A bypass capacitor must connect from LDO_5V to PGND. See Internal LDO Regulators for more information on LDO_5V.
  • LDO_3V3: Analog circuitry power supply. A bypass capacitor must connect from LDO_3V3 to AGND. See Internal LDO Regulators for more information on LDO_3V3.
  • BOOT1: Provides gate drive for M1. A bootstrap capacitor must connect from BOOT1 to SW1.
  • BOOT2: Provides gate drive for M3. A bootstrap capacitor must connect from BOOT2 to SW2.
  • SW1: Connects M1 and M2 to external inductor.
  • SW2: Connects M3 and M4 to external inductor.
  • CSP: Positive terminal of average current sense amplifier. Connects to positive terminal of output bulk capacitor.
  • CSN/BUS: Negative terminal of average current sense amplifier. A 10-mΩ current sense resistor is externally connected from CSP to CSN/BUS.

Depending upon the input voltage VIN and the output voltage VOUT, the converter can operate in one of four different states, each of which is described in following sections.

GUID-20201216-CA0I-T2GS-CM4Z-DF2KLKF6JNGC-low.gif Figure 9-7 Buck-Boost Internal Power FETs

Buck State

When the input voltage VIN significantly exceeds the output voltage VOUT, the converter enters the buck region of operation in which it performs an endless series of buck switching cycles Buck State. M3 and M5 are constantly on and M4 is constantly off. When the clock signals that a switching cycle has begun, the controller turns on M2 and turns off M1. This switch configuration corresponds to the off-time interval of a traditional buck converter. The voltage difference VSW1 – VSW2 across the inductor equals –VOUT. The inductor current IL ramps down until it reaches a threshold IVALLEY set by the error amplifiers. The controller then turns off M2 and turns on M1. This switch configuration corresponds to the on-time interval of a traditional buck converter. The voltage difference VSW1 – VSW2 now equals VIN – VOUT. The inductor current now ramps up until the converter clock signals that the end of the switching cycle has been reached.

The on-time ton equals the time interval during which M1 conducts. The off-time toff equals the time interval during which M2 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff. During the buck state, the controller regulates power flow by adjusting the buck duty cycle D, which equals the ratio ton/τ.

GUID-276435C1-4478-4266-B91E-04633F9FB0ED-low.gifFigure 9-8 Buck State

Buck Transition State

When the input voltage VIN is only slightly larger than the output voltage VOUT, the converter enters the buck transition region of operation in which it alternately performs buck and boost switching cycles Buck Transition. M5 is always on. When the clock signals that a buck switching cycle has begun, the controller turns on M2 and M3, and it turns off M1 and M4. This switch configuration corresponds to the off-time of a traditional buck converter. The inductor current IL ramps down until it reaches a threshold IVALLEY set by the error amplifiers. The controller then turns off M2 and turns on M1. This switch configuration corresponds to the on-time of a traditional buck converter. The inductor current now ramps up slowly until the clock signals the end of the buck switching cycle. The next switching cycle is a boost switching cycle. When this cycle begins, the controller turns M3 off and turns M4 on. M2 remains off, and both M1 and M5 remain on. This switch configuration corresponds to the on-time of a traditional boost converter. The inductor current IL now ramps up rapidly until the fixed on-time expires. The controller then turns off M4 and turns on M3. The inductor current now ramps down until the clock signals the end of the boost switching cycle. The next switching cycle will be another buck cycle.

During the buck transition state, the controller regulates power flow by adjusting the buck duty cycle. The boost duty cycle remains fixed. If the converter had remained in the buck state rather than move to the buck transition state, the buck on-time would have become so short that it would have become impossible to regulate power flow without pulse skipping.

GUID-06C7B3E9-6449-4B9E-BFCF-08CABACC79AE-low.gifFigure 9-9 Buck Transition

Boost Transition State

When the input voltage VIN is only slightly smaller than the output voltage VOUT, the converter enters the boost transition region of operation in which it alternately performs boost and buck switching cycles Boost Transition. M5 is always on. When the clock signals that a boost switching cycle has begun, the controller turns on M1 and M4, and it turns off M2 and M3. This switch configuration corresponds to the on-time of a traditional boost converter. The inductor current IL ramps up until it reaches a threshold IPEAK set by the error amplifiers. The controller then turns off M4 and turns on M3. This switch configuration corresponds to the off-time of a traditional boost converter. The inductor current now ramps down slowly until the clock signals the end of the boost switching cycle. The next switching cycle is a buck switching cycle. When this cycle begins, the controller turns M1 off and turns M2 on. M4 remains off, and both M3 and M5 remain on. This switch configuration corresponds to the off-time of a traditional buck converter. The inductor current IL now ramps down rapidly until the fixed off-time expires. The controller then turns off M2 and turns on M1. The inductor current now ramps up until the clock signals the end of the buck switching cycle. The next switching cycle will be another boost cycle.

During the boost transition state, the controller regulates power flow by adjusting the boost duty cycle. The buck duty cycle remains fixed. If the converter had remained in the boost state rather than move to the boost transition state, the boost on-time would have become so short that it would have become impossible to regulate power flow without pulse skipping.

GUID-CD6920EA-4CCE-4312-8B13-9319B746601C-low.gifFigure 9-10 Boost Transition

Boost State

When the input voltage VIN is significantly less than the output voltage VOUT, the converter enters the boost region of operation in which it performs an endless series of boost switching cycles Boost State. M1 and M5 are constantly on and M2 is constantly off. When the clock signals that a switching cycle has begun, the controller turns on M4 and turns off M3. This switch configuration corresponds to the on-time interval of a traditional boost converter. The voltage difference VSW1 – VSW2 across the inductor equals VIN. The inductor current IL ramps up until it reaches a threshold IPEAK set by the error amplifiers. The controller then turns off M4 and turns on M3. This switch configuration corresponds to the off-time interval of a traditional boost converter. The voltage difference VSW1 – VSW2 now equals VIN – VOUT, which is negative. The inductor current now ramps down until the converter clock signals that the end of the switching cycle has been reached.

The on-time ton equals the time interval during which M4 conducts. The off-time toff equals the time interval during which M3 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff. During the boost state, the controller regulates power flow by adjusting the boost duty cycle D, which equals the ratio ton/τ.

GUID-531B826C-E948-49D8-9F34-B9B96FB116AD-low.gifFigure 9-11 Boost State

Boundaries of the Regions of Operation

Regions of Operation graphically depicts the four regions of operation and the boundaries between them. When VBUS > kVIN, the converter remains in the boost region of operation. The value k is 1.2. When VIN < VBUS < kVIN, the converter enters the boost transition region of operation. When VIN/k < VBUS < VIN, the converter enters the buck transition region of operation. When VBUS < VIN/k, the converter enters the buck region of operation. The converter will cease operating if VIN exceeds the OVP threshold, which lies between 18 and 20 V. Similarly, the converter will also cease operating if VIN drops below either the internal UVLO threshold, which lies between 5 and 5.5 V, or the user programmed EN/UVLO threshold (see VIN UVLO and ENABLE/UVLO, whichever is greater).

GUID-A6B19B4E-E744-455B-A72F-5323B1963A60-low.gifFigure 9-12 Regions of Operation