JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Buck-Boost Regulator

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN)
IQ VIN shutdown current VEN/UVLO = 0 V 130 µA
IQ VIN operating current VEN/UVLO = 2V, VOUT = 5 V, IOUT = 0 A 8 mA
IQ VIN operating current VEN/UVLO = 1V, VOUT = 0 V, IOUT = 0 A 4.5 mA
IQ VIN operating current VEN/UVLO = 2V, VOUT = 0 V, IOUT = 0 A 8 mA
VIN(OVP_R) VIN rising overvoltage threshold VIN rising.  18.4 19.2 20 V
VIN(OVP_F) VIN falling overvoltage threshold VIN falling.  18.0 18.8 19.6 V
hysteresis 0.4 V
VIN(UVLO_R) VIN undervoltage lockout rising VIN rising.  5.14 5.30 5.46 V
VIN(UVLO_F) VIN undervoltage lockout falling VIN falling.  5.04 5.20 5.36 V
hysteresis 0.1 V
LDO_5V OUTPUT
VLDO_5V LDO_5V Output Regulation voltage 7V ≤ VIN ≤ 18 V, 0 < ILDO_5V < 125mA, VEN = 2 V. 4.5 4.63 4.75 V
VLDO_5V(UVLO_R) LDO_5V Undervoltage lockout rising 4.29 4.4 4.51 V
VLDO_5V(UVLO_F) LDO_5V Undervoltage lockout falling 4.09 4.2 4.31 V
Undervoltage hysteresis 200 mV
VLDO_5V_DO drop out voltage VIN = 5.5 V; ILDO_5V = 125mA 4.3 V
ILDO_5V(ILIMIT) LDO_5V current limit VLDO_V5V = 0 to 3.5 V, RLDO_V5V_LOAD = 1 Ω 125 200 400 mA
LDO_3V3 OUTPUT
VLDO_3V3 LDO_3V3 Output regulation voltage 7V ≤ VIN ≤ 18 V, VEN = 2 V, VLDO_5V(UVLO) < VLDO_5V < 5.5 V, 0 < ILDO_3V3 < 25mA 3.4 3.5 3.6 V
VLDO_3V3(UVLO_R) LDO_3V3 Undervoltage lockout rising 3.2 3.3 3.4 V
VLDO_3V3(UVLO_F) LDO_3V3 Undervoltage lockout falling 3.05 3.15 3.25 V
Undervoltage hysteresis 150 mV
VLDO_3V3_DO drop out voltage VIN = 4.5 V, ILDO_3V3 = 30mA 3.3 V
ILDO_3V3(ILIMIT) LDO_3V3 current limit VLDO_3V3 = 0 to 2.5 V, RLDO_3V3_LOAD = 1 Ω 35 50 80 mA
LDO_1V5 OUTPUT
VLDO_1V5 LDO_1V5 Output Regulation voltage 4.5 < VLDO_5V < 5.5V, 0 < ILDO_1V5 < 10 mA 1.49 1.55 1.65 V
VLDO_1V5(UVLO_R) LDO_1V5 Undervoltage lockout rising 1.44 1.49 1.54 V
VLDO_1V5(UVLO_F) LDO_1V5 Undervoltage lockout falling 1.37 1.42 1.47 V
Undervoltage hysteresis 70 mV
ILDO_1V5(ILIMIT) LDO_1V5 current limit VLDO_1V5 = 0 to 1.2 V, RLDO_1V5_LOAD = 1 Ω 15 20 28 mA
EN/UVLO
VEN(LDO_V5V_R) EN input level required to turn on internal LDOs EN/UVLO rising 1.05 V
VEN(LDO_V5V_F) EN input level required to turn off internal LDOs EN/UVLO falling 0.3 V
VEN(OPER) EN input level required to start operation EN/UVLO rising Precision EN 1.2 1.25 1.3 V
VEN(STBY) EN input level required to stop operation EN/UVLO falling 1.1 1.15 1.2 V
VEN(HYS) Hysteresis 100 mV
VEN(CLAMP) EN input clamp voltage VEN/UVLO > VEN(CLAMP), 10 µA < IEN/UVLO  < 1 mA 6 9 12 V
IEN(LEAK) Leakage current into EN pin 0 V < VEN < 6 V 1 µA
OUTPUT VOLTAGE
VCSN/BUS(3V) VCNS/BUS regulation accuracy at 3V 0 ≤ IOUT ≤ 3A 2.9 3 3.1 V
VCSN/BUS(5V) VCNS/BUS regulation accuracy at 5V 0 ≤ IOUT ≤ 3A 4.85 5 5.15 V
VCSN/BUS(21V) VCNS/BUS regulation accuracy at 21V 0 ≤ IOUT ≤ 3A 20.48 21 21.53 V
VCSN/BUS_STP Output voltage step size (12-bit DAC) 10 mV
VDAC Resolution Resolution of VBUS DAC 12 Bits
IDISCHG CSN/BUS discharge current when transitioning to VSafe0V VCSP = VCSN/BUS. VCSN/BUS = 3V. Measure current into BUS.  40 mA
tDISCHG CSN/BUS discharge time when transitioning to VSafe5V VBUS = 21 V (max), CBULK = 220 µF, time to discharge BUS to < 5.5 V (per USB PD specification) 275 ms
tDISCHG CSN/BUS discharge time when transitioning to VSafe0V VBUS = 21 V (max), CBULK = 220 µF, time to discharge BUS to < 0.8 V (per USB PD specification) 650 ms
RDISCHG Weak discharge resistance on BUS pin when not sourcing VBUS EN = 2V; measure BUS to PGND resistance. 60 135 kΩ
RBUS-GND(PWR) BUS to GND resistance, RDISCH disabled, not sourcing VBUS EN = 2V measure BUS to PGND resistance. 120 500 kΩ
RBUS-GND(UNPWR) BUS to GND resistance, unpowered VIN = EN = 0V measure BUS to PGND resistance. 2 kΩ
CABLE VOLTAGE DROP COMPENSATION
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.1V/A: VCSP - VCSN/BUS = 50 mV 465 500 535 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.1V/A: VCSP - VCSN/BUS = 10 mV 85 100 115 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain stetting = 0.075V/A: VCSP - VCSN/BUS = 50 mV 346 375 404 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.075V/A: VCSP - VCSN/BUS = 10 mV 61 75 89 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.05V/A: VCSP - VCSN/BUS = 50 mV 227 250 273 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.05V/A: VCSP - VCSN/BUS = 10 mV 37 50 63 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.025V/A: VCSP - VCSN/BUS = 50 mV 109 125 141 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.025V/A: VCSP - VCSN/BUS = 10 mV 14 25 36 mV
VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0V/A: 0 mV ≤ VCSP -VCSN/BUS ≤ 50 mV -5 20 mV
BUCK-BOOST PEAK CURRENT LIMITS
IPEAK(BOOST) Boost peak current limit (in boost mode) 12.3 14.5 16.7 A
IPEAK(BOOST) Boost peak current limit (in boost mode) 10.8 12.8 14.7 A
IPEAK(BOOST) Boost peak current limit (in boost mode) 9.3 11.0 12.6 A
IPEAK(BOOST) Boost peak current limit (in boost mode) 7.9 9.3 10.6 A
IPEAK(BOOST) Boost peak current limit (in boost mode) 6.3 7.5 8.6 A
IPEAK(BOOST) Boost peak current limit (in boost mode) 4.8 5.7 6.5 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 8.2 9.7 11.2 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 9.0 10.6 12.1 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 9.7 11.4 13.1 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 10.4 12.3 14.1 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 5.3 6.2 7.2 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 6 7.1 8.2 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 6.8 8.0 9.1 A
IPEAK(BUCK) Buck peak current limit (in buck mode) 7.5 8.8 10.1 A
INEG(BUCK) Buck negative current limit (in buck mode) -4.6 - 3.8 -3 A
OUT CURRENT DAC
IDAC_Resolution 8 Bits
CURRENT LIMIT
ILIMIT_LO Current limit accuracy  1 A ≤ IOUT ≤ 3 A, VCSN/BUS < 2.5 V; RS = 10 mΩ.  -250 250 mA
ILIMIT_LO Current limit accuracy < 1 A 1 A ≤ IOUT ≤ 3 A, VCSN/BUS ≥ 2.5 V; RS = 10 mΩ -150 150 mA
ILIMIT_HI Current limit accuracy > 3 A IOUT > 3 A, VCSN/BUS < 2.5 V; RS = 10 mΩ -20 20 %
ILIMIT_HI Current limit accuracy > 3 A IOUT > 3 A, VCSN/BUS ≥ 2.5 V; RS = 10 mΩ -5 5 %
ILIMIT_MIN Minimum programmable current limit 1 A
ICL_STEP Current limit step size 1 A ≤ IOUT ≤ 5 A; RS = 10 mΩ 50 mA
FREQUENCY
fSW(1) Switching Frequency 1 285 300 315 kHz
fSW(2) Switching Frequency 2  380 400 420 kHz
fSW(3) Switching Frequency 3  428 450 473 kHz
FREQUENCY DITHER
FSSS Positive frequency deviation during dither 8 10 12 %
Negative frequency deviation during dither -12 -10 -8 %
FSSS_MOD Modulation frequency of dither DITHER_FREQ = 0 9 10 11 kHz
FSSS_MOD Modulation frequency of dither DITHER_FREQ = 1 22.5 25 27.5 kHz
OVERVOLTAGE PROTECTION
VCSN/BUS_OVP_R Fixed output overvoltage threshold at CSN/BUS pin 22.0 23 24 V
VCSN/BUS_OVP_F Falling 20.5 21.5 22.5 V
Hysteresis 1.5 V
POWER SWITCHES
RDS(ON) M1 VIN = 12V; (VBOOT1 - VSW1) = 4.5V; ISW1 = -1 A 4.5 mΩ
RDS(ON) M2 VIN = 12V; ISW1 = 1 A 20 mΩ
RDS(ON) M4 VIN = 12V; ISW2 = 1 A  6 mΩ
RDS(ON) M3 + M5 VIN = VOUT = 12V: (VBOOT2 - VSW2) = 4.5V, ISW2 = -1 A  18 mΩ
VUV_BOOT1_R BOOT1 to SW1 rising UVLO threshold 3.5 4 4.4 V
VUV_BOOT1_F BOOT1 to SW1 falling UVLO threshold



 		 2.9 3.4 3.7 V
BOOT1 to SW1 UVLO hysteresis 680 mV
VOV_BOOT1_R BOOT1 to SW1 rising OVP threshold 4.6 5.3 5.9 V
VOV_BOOT1_F BOOT1 to SW1 falling OVP threshold 4.3 5 5.6 V
BOOT 1 OVP hysteresis 250 300 350 mV
VUV_BOOT2_R BOOT2 to SW2 rising UVLO threshold 3.5 4 4.4 V
VUV_BOOT2_F BOOT2 to SW2 falling UVLO threshold 2.9 3.4 3.7 V
BOOT2 to SW2 UVLO hysteresis 680 mV
VOV_BOOT2_R BOOT2 to SW2 rising OVP threshold 4.6 5.3 5.9 V
VOV_BOOT2_F BOOT2 to SW2 falling OVP threshold 4.3 5 5.6 V
BOOT2 OVP hysteresis 250 300 350 mV
BUCK-BOOST CHARACTERISTICS
tSS Soft-start time 6 ms
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.