JAJSD32 April   2017 TPS25810A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 USB Type-C Basic
      2. 8.1.2 Configuration Channel
      3. 8.1.3 Detecting a Connection
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Configuration Channel Pins CC1 and CC2
      2. 8.3.2 Current Capability Advertisement and Overload Protection
      3. 8.3.3 Undervoltage Lockout (UVLO)
        1. 8.3.3.1  Device Power Pins (IN1, IN2, AUX, OUT, and GND)
        2. 8.3.3.2  FAULT Response
        3. 8.3.3.3  Thermal Shutdown
        4. 8.3.3.4  REF
        5. 8.3.3.5  Audio Accessory Detection
        6. 8.3.3.6  Debug Accessory Detection
        7. 8.3.3.7  Plug Polarity Detection
        8. 8.3.3.8  Device Enable Control
        9. 8.3.3.9  Cable Compensation (CS)
        10. 8.3.3.10 Power Wake
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Type-C DFP Port Implementation Without BC 1.2 Support
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Input and Output Capacitance
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
      2. 12.2.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range, voltages are with respect to GND (unless otherwise noted) (1)
MIN MAX UNIT
Pin voltage, V AUDIO, AUX, CC1, CC2, CHG, CHG_HI, CS, DEBUG, EN, FAULT, IN1, IN2, OUT, POL, REF, UFP, –0.3 7 V
REF_RTN Internally connected to GND V
Pin positive source current, ISRC CC1, CC2, OUT, REF Internally limited A
Pin positive sink current, ISNK OUT (while applying VBUS) 5 A
CC1, CC2 (while applying VCONN) 1 A
AUDIO, CS, DEBUG, FAULT, POL, UFP Internally limited mA
Operating junction temperature, TJ –40 180 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD)(1) Electrostatic discharge Human-body model (HBM), per per AEC Q100-002(2) ±2 000 V
Charged-device model (CDM), per per AEC Q100-011 ±500
61000-4-2 contact discharge, CC1 and CC2(3) IEC ±8 000
IEC 61000-4-2 air discharge, CC1 and CC2(3) ±15 000
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(3) Surges per IEC61000-402, 1999 applied between CC1, CC2 and output ground of the TPS25810EVM-745.

7.3 Recommended Operating Conditions

Voltages are with respect to GND (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply voltage IN1 4.5 6.5 V
IN2 4.5 5.5
AUX 2.9 5.5
VI Input voltage CHG, CHG_HI, EN 0 5.5 V
VIH High-level input voltage CHG, CHG_HI, EN 1.17 V
VIL Low-level voltage CHG, CHG_HI, EN 0.63 V
VPU Pullup voltage Used on AUDIO, CS, DEBUG, FAULT, POL, UFP, 0 5.5 V
ISRC Positive source current OUT 3 A
CC1 or CC2 when supplying VCONN 250 mA
ISNK Positive sink current (10 ms moving average) AUDIO, CS, DEBUG, FAULT, POL, UFP 10 mA
ISNK_PULSE Positive repetitive pulse sink current AUDIO, CS, DEBUG, FAULT, POL, UFP Internally limited mA
RREF Reference resistor 98 100 102 kΩ
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS25810A-Q1 UNIT
RVC (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43.4 °C/W
RθJB Junction-to-board thermal resistance 13 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 13 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF = 100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT – POWER SWITCH
rDS(on) On-resistance(1) TJ = 25°C, IOUT = 3 A 34 37 mΩ
–40°C ≤ TJ ≤ 85°C, IOUT = 3 A 34 46
–40°C ≤ TJ ≤ 125°C, IOUT = 3 A 34 55
IREV OUT to IN reverse leakage current VOUT = 6.5 V, VIN1 = VEN = 0 V,
–40°C ≤ TJ ≤ 85°C,
IREV is current out of IN1 pin 		0 3 µA
OUT – CURRENT LIMIT
IOS Short-circuit current limit (1) 3.16 3.4 3.64 A
RREF = 10 Ω 7
OUT – DISCHARGE
Discharge resistance VOUT = 4 V, UFP signature removed from CC lines, time < tw_DCHG 400 500 600 Ω
Bleed discharge resistance VOUT = 4 V, No UFP signature on CC lines, time > tw_DCHG 100 150 250 kΩ
REF
VO Output voltage 0.78 0.8 0.82 V
IOS Short circuit current RREF = 10 Ω 9.5 15.3 µA
FAULT
VOL Output low voltage IFAULT = 1 mA 350 mV
IOFF Off-state leakage VFAULT = 5.5 V 1 µA
CS
VOL Output low voltage ICS = 1 mA 350 mV
IOFF Off-state leakage VCS = 5.5 V 1 µA
ITH OUT sourcing, rising threshold current for load detect 1.8 1.95 2.1 A
Hysteresis(2) 125 mA
CC1, CC2 – VCONN POWER SWITCH
rDS(on) On-resistance TJ = 25°C, IOUT = 250 mA 365 420 mΩ
–40°C ≤ TJ ≤ 85°C, IOUT = 250 mA 365 530
–40°C ≤ TJ ≤ 125°C, IOUT = 250 mA 365 600
CC1, CC2 – VCONN POWER SWITCH – CURRENT LIMIT
IOS Short-circuit current limit(1) 300 355 410 mA
RREF = 10 Ω 800
CC1, CC2 – CONNECT MANAGEMENT – DANGLING ELECTRONICALLY MARKED CABLE MODE
ISRC Sourcing current on the pass-through CC Line 0 V ≤ VCCx ≤ 1.5 V 64 80 96 µA
Sourcing current on the Ra CC line 0 V ≤ VCCx ≤ 1.5 V 64 80 96
CC1, CC2 – CONNECT MANAGEMENT – ACCESSORY MODE
ISRC CCx sourcing current
(CC2 – audio, CC1-debug) 		0 V ≤ VCCx ≤ 1.5 V 64 80 96 µA
CCx sourcing current
(CC1 – audio, CC2-debug) (2)		 0 V ≤ VCCx ≤ 1.5 V 0
CC1, CC2 – CONNECT MANAGEMENT – UFP MODE
ISRC Sourcing current with either IN1 or IN2 in UVLO 0 V ≤ VCCx ≤ 1.5 V
VIN1 < VTH_UVLO_IN1 or VIN2 < VTH_UVLO_IN2		 64 80 96 µA
ISRC Sourcing current VCHG = 0 V and VCHG_HI = 0 V
0 V ≤ VCCx ≤ 1.5 V 		75 80 85 µA
VCHG = VAUX and VCHG_HI = 0 V
0 V ≤ VCCx ≤ 1.5 V 		170 180 190
VCHG = VAUX and VCHG_HI = VAUX
0 V ≤ VCCx ≤ 2.45 V 		312 330 348
UFP, POL, AUDIO, DEBUG
VOL Output low voltage ISNK_PIN = 1 mA 250 mV
IOFF Off-state leakage VPIN = 5.5 V 1 µA
EN, CHG, CHG_HI – LOGIC INPUTS
VTH Rising threshold voltage 0.925 1.15 V
VTH Falling threshold voltage 0.65 0.875 V
Hysteresis(2) 50 mV
IIN Input current VEN = 0 V or 6.5 V –0.5 0.5 µA
OVERTEMPERATURE SHUTDOWN
TTH_OTSD2 Rising threshold temperature for device shutdown 155 °C
Hysteresis(2) 20 °C
TTH_OTSD1 Rising threshold temperature for OUT/ VCONN switch shutdown in current limit 135 °C
Hysteresis(2) 20 °C
IN1
VTH_UVLO_IN1 Rising threshold voltage for UVLO 3.9 4.1 4.3 V
Hysteresis(2) 100 mV
IIN1(DIS) Disabled supply current VEN = 0 V, –40°C ≤ TJ ≤ 85°C 1 µA
IIN1(CC_OPEN) Enabled supply current with CC lines open –40°C ≤ TJ ≤ 85°C 1 µA
IIN1(Ra) Enabled supply current with accessory or dangling electronically marked cable signature on CC lines 2 µA
IIN1(Rd) Enabled supply current with UFP attached VCHG = 0 V, or VCHG = VAUX and VCHG_HI = 0 V 75 100 µA
85 110
IN2
VTH_UVLO_IN2 Rising threshold voltage for UVLO 3.9 4.1 4.3 V
Hysteresis(2) 100 mV
IIN2(DIS) Disabled supply current VEN = 0 V, –40°C ≤ TJ ≤ 85°C 1 µA
IIN2(CC_OPEN) Enabled supply current with CC lines open –40°C ≤ TJ ≤ 85°C 1 µA
IIN2(Ra) Enabled supply current with accessory or dangling electronically marked cable signature on CC lines 2 µA
IIN2(Rd) Enabled supply current with UFP signature on CC lines
(Includes IN current that provides the CC output current to the UFP Rd resistor) 		VCHG = 0 V, 0 V ≤ VCCx ≤ 1.5 V 98 110 µA
VCHG = VIN and VCHG_HI = 0 V, 0 V ≤ VCCx ≤ 1.5 V 198 215
0 V ≤ VCCx ≤ 2.45 V 348 373
AUX
VTH_UVLO_AUX Rising threshold voltage for UVLO 2.65 2.75 2.85 V
Hysteresis(2) 100 mV
IAUX(DIS) Disabled supply current VEN = 0 V, –40°C ≤ TJ ≤ 85°C 1 µA
IAUX(CC_OPEN) Enabled internal supply current with CC lines open –40°C ≤ TJ ≤ 85°C 0.7 3 µA
IAUX(Ra) Enabled supply current with accessory or dangling active cable signature on CC lines 140 185 µA
IAUX(Rd_noIN) Enabled supply current with UFP termination on CC lines and with either IN1 or IN2 in UVLO VIN1 < VTH_UVLO_IN1 or VIN2 < VTH_UVLO_IN2 145 190 µA
IAUX(Rd) Enabled supply current with UFP termination on CC lines 55 82 µA
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
(2) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product warranty.

7.6 Switching Characteristics

–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF = 100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT – POWER SWITCH
tr Output-voltage rise time VIN1 = 5 V, CL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value) 1.2 1.8 2.5 ms
tf Output-voltage fall time 0.35 0.55 0.75 ms
ton Output-voltage turnon time VIN1 = 5 V, CL = 1 µF, RL = 100 Ω 2.5 3.5 5 ms
toff Output-voltage turnoff time 2 3 4.5 ms
OUT – CURRENT LIMIT
tios Current-limit response time to short circuit VIN1 – VOUT = 1 V, RL = 10 mΩ, see Figure 1 1.5 4 µs
FAULT
tDEGA Asserting deglitch time due to overcurrent 5.5 8.2 10.7 ms
tDEGA(OC) Asserting deglitch time due to overtemperature in current limit(1) 0 ms
tDEGA(OT) Deasserting deglitch time 5.5 8.2 10.7 ms
CS
tDEGA Asserting deglitch time 5.5 8.2 10.7 ms
tDEGD Deasserting deglitch time 5.5 8.2 10.7 ms
OUT – DISCHARGE
RDCHG discharge time VOUT = 1 V, time ISNK_OUT > 1 mA after UFP signature removed from CC lines 39 65 96 ms
CC1, CC2 - VCONN POWER SWITCH
tr Output-voltage rise time VIN2 = 5 V, CL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value) 0.15 0.25 0.35 ms
tf Output-voltage fall time 0.18 0.22 0.26 ms
ton Output-voltage turnon time VIN2 = 5 V, CL = 1 µF, RL = 100 Ω 1 1.5 2 ms
toff Output-voltage turnoff time 0.3 0.4 0.55 ms
CC1, CC2 – VCONN POWER SWITCH – CURRENT LIMIT
tres Current-limit response time to short circuit VIN2 – VCONN = 1 V, R = 10 mΩ, see Figure 1 1 3 µs
UFP, POL, AUDIO, DEBUG
tDEGR Asserting deglitch time 100 150 200 ms
tDEGF Deasserting deglitch time 7.9 12.5 17.7 ms
(1) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product warranty.
TPS25810A-Q1 OSCP_SLVSD95.gif Figure 1. Output Short-Circuit Timing Diagram

7.7 Typical Characteristics

TPS25810A-Q1 D001_SLVSCR1.gif
Figure 2. VBUS Current-Limiting Switch On-Resistance vs Temperature
TPS25810A-Q1 D003_SLVSCR1.gif
Device disabled (VOUT – VIN) = 6.5 V
Figure 4. OUT Reverse Leakage Current vs Temperature
TPS25810A-Q1 D005_SLVSE37.gif
Figure 6. CS Threshold vs Temperature
TPS25810A-Q1 D007_SLVSCR1.gif
Figure 8. IN1 Current With UFP vs Temperature
TPS25810A-Q1 D009_SLVSCR1.gif
VAUX = 5 V
Figure 10. AUX Current With UFP vs Temperature
TPS25810A-Q1 D002_SLVSCR1.gif
Figure 3. VCONN Current-Limiting Switch On-Resistance vs Temperature
TPS25810A-Q1 D004_SLVSCR1.gif
Figure 5. ILIM for VBUS and VCONN vs Temperature
TPS25810A-Q1 D006_SLVSCR1.gif
Figure 7. CC Sourcing Current to UFP vs Temperature
TPS25810A-Q1 D008_SLVSCR1.gif
Figure 9. IN2 Current With UFP vs Temperature