JAJSJU4D May   2020  – September 2021 TPS25850-Q1 , TPS25851-Q1 , TPS25852-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Enable On/Off Control (TPS25852-Q1)
      14. 10.3.14 FAULT Indication (TPS25851-Q1 and TPS25852-Q1)
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Plug Polarity Detection (TPS25851-Q1)
      17. 10.3.17 USB Port Operating Modes
        1. 10.3.17.1 USB Type-C® Mode
        2. 10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25850-Q1 Only)
          1. 10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.17.2.2 DCP Divider-Charging Scheme
          3. 10.3.17.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.17.3 DCP Auto Mode (TPS25850-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Timing Requirements

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)
MIN NOM MAX UNIT
POL(TPS25851-Q1)
tDEGLA_POL Asserting deglitch time 100 150 200 ms
tDEGLD_POL De-asserting deglitch time 8.2 12.5 18 ms
FAULT (TPS25851/2-Q1)
tDEGLA_FAULT Asserting deglitch time (Thermal SD Fault assertion is instantaneous, not subject to this timing) 2.94 4.1 5.42 ms
tDEGLD_FAULT De-asserting deglitch time 11.09 16.38 23.03 ms
BUS DISCHARGE
tDEGA_BUS_DCHG Discharge asserting deglitch 5.6 12.3 21.2 ms
tW_BUS_DCHG VBUS discharge time after sink termination removed from CC lines VBUS = 1 V, time ISNK_OUT > 1 mA after sink termination removed from CC lines 170 260 360 ms
POWER SWITCH TIMING
tIOS_HI_DEG Deglitch time for USB power switch current limit enable USB port enter overcurrent (per ILIM setting) 1.228 2.048 2.867 ms
tIOS_HI_RST MFI OCP reset timing 9.6 16 22.4 ms
tr_USB PA_BUS, PB_BUS, BUS voltage rise time CL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value) 1.67 ms
tf_USB PA_BUS, PB_BUS, BUS voltage fall time CL = 1 µF, RL = 100 Ω (measured from 90% to 10% of final value) 0.49 ms
ton_USB PA_BUS, PB_BUS, BUS voltage turnon-time CL = 1 µF, RL = 100 Ω 2.59 ms
toff_USB PA_BUS, PB_BUS, BUS voltage turnoff-time CL = 1 µF, RL = 100 Ω 2.07 ms
tIOS_USB PA_BUS, PB_BUS, BUS short-circuit response time CL = 1 µF, RL = 1 Ω 1 us
tr_OUT OUT voltage rise time CL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value) 0.12 0.2 0.28 ms
tf_OUT OUT voltage fall time CL = 1 µF, RL = 100 Ω (measured from 90% to 10% of final value) 0.16 0.22 0.28 ms
ton_OUT OUT voltage turnon-time CL = 1 µF, RL = 100 Ω 0.6 1.1 1.65 ms
toff_OUT OUT voltage turnoff-time CL = 1 µF, RL = 100 Ω 0.45 0.54 0.62 ms
tIOS_OUT OUT short-circuit response time CL = 1 µF, RL = 1 Ω 1.4 4 us
tIOS_VCONN  CC-VCONN short circuit response time CL = 1 µF, RL = 1 Ω 1 3.5 µs
tr_VCONN VCONN output voltage rise time CL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value); 5.1KΩ on CC1 and 1KΩ on CC2 0.2 0.28 0.36 ms
tf_VCONN VCONN output voltage fall time CL = 1 µF, RL = 100 Ω (measured from 90% to 10% of final value); 5.1KΩ on CC1 and 1KΩ on CC2 0.18 0.23 0.28 ms
ton_VCONN VCONN output voltage turnon time CL = 1 µF, RL = 100 Ω; 5.1KΩ on CC1 and 1KΩ on CC2 0.7 1.2 1.7 ms
toff_VCONN VCONN output voltage turnoff time CL = 1 µF, RL = 100 Ω; 5.1KΩ on CC1 and 1KΩ on CC2 0.37 0.44 0.51 ms
HICCUP MODE
THICP_ON OUT, PA_BUS, PB_BUS output hiccup mode ON time OC, VOUT, VPA_BUS, VPB_BUS drop 10% 2.94 4.1 5.42 ms
THICP_OFF OUT, PA_BUS, PB_BUS output hiccup mode OFF time OC, OUT, PA_BUS, PB_BUS connect to GND 367 524 715 ms