JAJSMR0 August   2021 TPS25860-Q1 , TPS25862-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management with Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Enable On/Off Control (TPS25862-Q1)
      14. 10.3.14 FAULT Indication
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
      17. 10.3.17 USB Port Operating Modes
        1. 10.3.17.1 USB Type-C® Mode
        2. 10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25860-Q1 Only)
          1. 10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.17.2.2 DCP Divider-Charging Scheme
          3. 10.3.17.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.17.3 DCP Auto Mode (TPS25860-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
        9. 11.2.2.9 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.4 FREQ/SYNC

The switching frequency of the TPS2586x-Q1 can be programmed by the resistor RFREQ from the FREQ/SYNC pin and AGND pin. To determine the FREQ resistance, for a given switching frequency, use Equation 4.

Equation 4. GUID-6FC3538B-5D96-4081-83BC-9969D8121B19-low.gif
GUID-92554BBE-5E0B-44E8-9742-C7C1E36314AA-low.gif Figure 10-3 FREQ Set Resistor vs Switching Frequency

The normal method of setting the buck regulator switching frequency is by selecting an appropriate value FREQ resistor as shown in Table 10-1.

Table 10-1 Setting the Switching Frequency with FREQ
FREQ (KΩ)SWITCHING FREQUENCY (KHz)
80.6253
49.9400
19.11000
8.872100
8.452200

The FREQ/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the FREQ/SYNC pin. When using a low impedance signal source, the frequency setting resistor FREQ is connected in parallel with an AC coupling capacitor, CCOUP, to a termination resistor, RTERM (for example, 50 Ω). The two resistors in series provide the default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used for CCOUP. The AC coupled peak-to-peak voltage at the FREQ/SYNC pin must exceed the SYNC amplitude threshold of 1.2 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock HIGH and LOW time must be longer than 100 ns (typical). A 2.5 V or higher amplitude pulse signal coupled through a 1-nF capacitor, CSYNC, is a good starting point. Figure 10-4 shows the device synchronized to an external system clock. The external clock must be off before start-up to allow proper start-up sequencing.

GUID-94ED8184-09C8-4483-8401-4F4BA1DEC318-low.pngFigure 10-4 Synchronize to External Clock

The TPS2586x-Q1 switching action can be synchronized to an external clock from 200 KHz to 3 MHz. Even the switching frequency can be set to higher than 2.4 MHz, but it is recommend to set the switching frequency below 2.4 MHz due to the power dissipation, the higher switching frequency results in more power loss on IC, cause the junction temperature and also the board temperature rising, then the device may enter load shedding under high ambient temperature.

Figure 10-5, Figure 10-6 and Figure 10-7 show the device switching frequency and behavior under different VIN voltage and RFREQ = 8.45 kΩ.

Figure 10-8, Figure 10-9 and Figure 10-10 show the device switching frequency and behavior under different VIN voltage and synchronized to an external 2.2-MHz system clock.

GUID-20201005-CA0I-7W2H-THSC-SPMRLSK69PP4-low.gif
VIN = 8 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-5 Switching Frequency When RFREQ = 8.45 kΩ
GUID-20201005-CA0I-MM5V-9RFP-ZXJZ3XHFRQGH-low.gif
VIN = 18 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-7 Switching Frequency When RFREQ = 8.45 kΩ
GUID-20201005-CA0I-FNZM-DWF6-JHMSGGF7D824-low.gif
VIN = 13.5 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-9 Synchronizing to External 2.2-MHz Clock
GUID-20201005-CA0I-FHBM-SP8W-SMBMCC6CXDG5-low.gif
VIN = 13.5 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-6 Switching Frequency When RFREQ = 8.45 kΩ
GUID-20201005-CA0I-KDPX-6RLM-DM92K9SCPH2V-low.gif
VIN = 8 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-8 Synchronizing to External 2.2-MHz Clock
GUID-20201005-CA0I-PHJ5-Q6HJ-ZGQJ9TBGJQFM-low.gif
VIN = 18 V L = 0.68 uH IPA_BUS = 3 A IPB_BUS = 2.4 A
Figure 10-10 Synchronizing to External 2.2-MHz Clock