JAJSMQ9 August   2021 TPS25868-Q1 , TPS25869-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management with Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Enable On/Off Control (TPS25869-Q1)
      14. 10.3.14 FAULT Indication
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
      17. 10.3.17 USB Port Operating Modes
        1. 10.3.17.1 USB Type-C® Mode
        2. 10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25868-Q1 Only)
          1. 10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.17.2.2 DCP Divider-Charging Scheme
          3. 10.3.17.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.17.3 DCP Auto Mode (TPS25868-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
        9. 11.2.2.9 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400kHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTATE (IN PIN)
ISD Shutdown quiescent current; measured at IN pin. VEN/UV = 0,  –40°C ≤ TJ ≤ 85°C 21 50 uA
VOVLO_R Voltage on VIN pin when buck regulator stops switching 26.6 27.5 28.4 V
VOVLO_HYS Hysteresis 0.5 V
ENABLE AND UVLO (EN/UVLO PIN)
VEN/UVLO_R Rising threshold for not in External UVLO VEN/UV rising threshold 1.26 1.3 1.34 V
VEN/UVLO_HYS Hysteresis VEN/UVLO falling 100 mV
VPA/B_EN_H PA_EN, PB_EN input level required to turn on PA_BUS and PB_BUS Load Switch VPA_EN or VPB_EN rising threshold 1.6 1.98 V
VPA/B_EN_L PA_EN, PB_EN input level required to turn off PA_BUS and PB_BUS Load Switch VPA_EN or VPB_EN falling threshold 0.97 1.5 V
VEN1/2_HYS Hysteresis VPA_EN or VPB_EN falling threshold 100 mV
BOOTSTRAP
VBTST_UVLO Bootstrap voltage UVLO threshold 2.2 V
RBOOT Bootstrap pull-up resistence VSENSE-BOOT = 0.1 V, Need a test mode 7.7 Ω
BUCK REGULATOR
IL-SC-HS High-side current limit BOOT-SW = 5 V 10.2 11.4 12.6 A
IL-SC-LS Low-side current limit SENSE = 5 V 8.5 10 11.5 A
IL-NEG-LS Low-side negative current limit SENSE = 5 V –5 A
IZC Zero current detector threshold 0.01 A
VSENSE BUCK Output voltage CC1 or CC2 pulldown resistance = Rd, VSET float or pull up to VSENSE, TJ  = 25℃ -1% 5.1 +1% V
CC1 or CC2 pulldown resistance = Rd, VSET short to AGND, TJ  = 25℃ -1% 5.17 +1% V
CC1 or CC2 pulldown resistance = Rd, RVSET = 40.2 KΩ, TJ  = 25℃ -1% 5.3 +1% V
CC1 or CC2 pulldown resistance = Rd, RVSET = 80.6 KΩ, TJ =25℃ -1% 5.4 +1% V
VSENSE BUCK Output voltage accuracy CC1 or CC2 pulldown resistance = Rd, –40℃ ≤ TJ  ≤ 150℃ –2 2 %
VDCDC_UVLO_R SENSE input level to enable DCDC switching VSENSE rising, CC1 or CC2 pull down resistance = Rd 3.85 4 4.15 V
VDCDC_UVLO_HYS Hysteresis VSENSE falling, CC1 or CC2 pull down resistance = Rd 0.4 V
VDROP Dropout voltage ( VIN-VSENSE ) VIN = VSENSE + VDROP, VSENS  = 5.1V, IPA_BUS = 3 A, IPB_BUS= 2.4 A 300 mV
RDS-ON-HS High-side MOSFET ON-resistance IPA_BUS=3A, IPB_BUS = 2.4 A, BOOT-SW = 5 V, –40℃ ≤ TJ  ≤ 150℃ 18 34 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IPA_BUS = 3 A, IPB_BUS = 2.4 A, VSENSE = 5 V, –40℃≤ TJ  ≤ 150℃ 9.5 18.5 mΩ
POWER SWITCH AND CURRENT LIMIT
RDS-ON_USB USB Load Switch MOSFET ON-resistance IPA_BUS = 3 A, IPB_BUS = 2.4 A; -40℃ ≤ TJ ≤ 150℃ 6.8 11.73 mΩ
RDS-ON_OUT OUT Load Switch MOSFET ON-resistance IOUT = 0.3 A 230 mΩ
RDS-ON_VCONN On-state resistance TJ = 25°C, ICCn = 0.25 A 410 550 mΩ
RDS-ON_VCONN On-state resistance –40°C ≤TJ ≤ 150°C, ICCn = 0.25 A 410 740 mΩ
VUSBLS_UVLO_R Voltage on SENSE pin that will enable the USB Load Switch 3.95 4.1 4.25 V
VUSBLS_UVLO_HYS Hysteresis 200 mV
RBUS_DCHG Discharge resistance for Port A or Port B BUS Apply 5 V on PA_BUS or PB_BUS, PA_EN or PB_EN pull low 250 500 750 Ω
VTH_R_BUS_DCHGb Rising threshold voltage for BUS not discharged   670 700 730 mV
VTH_HYS_BUS_DCHG Hysteresis   100 mV
VBUS_DCHG_BLEED BUS bleed resistance VPA_BUS = 4 V, No sink termination on CC lines, Time>tW_BUS_DCHG 100 150 200 KΩ
IOS_HI (USB Port B) Port B BUS output short-circuit secondary current limit RILIM = 48.7 KΩ 679 849 1018 mA
RILIM = 19.1 KΩ 1947 2163 2379 mA
RILIM = 15.4 KΩ 2415 2683 2951 mA
RILIM = 12.4 KΩ 2999 3332 3665 mA
RILIM = 11.5 KΩ 3233 3592 3951 mA
RILIM = 9.53 KΩ 3901 4334 4767 mA
RILIM= 0 Ω (short to GND) 3862 4544 5225 mA
RILIM= 11.5 KΩ, TJ  = 25℃ 3412 3592 3771 mA
IOS_BUS (USB Port B) Port B BUS output short-circuit current limit RILIM = 48.7 KΩ 424 530 636 mA
RILIM = 19.1 KΩ 1217 1352 1487 mA
RILIM= 15.4 KΩ 1509 1677 1844 mA
RILIM = 12.4 KΩ 1874 2082 2290 mA
RILIM = 11.5 KΩ 2020 2245 2469 mA
RILIM = 9.53 KΩ 2438 2709 2980 mA
RILIM= 0 Ω (short to GND) 2414 2840 3266 mA
RILIM = 11.5 KΩ, TJ  = 25℃ 2133 2245 2357 mA
IOS_HI (USB Port A) Port A BUS output short-circuit secondary current limit RILIM= 48.7 KΩ 849 1061 1273 mA
RILIM = 19.1 KΩ 2434 2704 2974 mA
RILIM = 15.4 KΩ 3018 3354 3689 mA
RILIM = 12.4 KΩ 3748 4165 4581 mA
RILIM = 11.5 KΩ 4040 4490 4938 mA
RILIM = 9.53 KΩ 4876 5418 5960 mA
RILIM= 0 Ω (short to GND) 4828 5680 6532 mA
RILIM = 11.5 KΩ, TJ  = 25℃ 4265 4490 4714 mA
IOS_BUS (USB Port A) Port A BUS output short-circuit current limit RILIM = 48.7 KΩ 530.4 663 795.6 mA
RILIM = 19.1 KΩ 1521 1690 1859 mA
RILIM = 15.4 KΩ 1886.4 2096 2305.6 mA
RILIM = 12.4 KΩ 2342.7 2603 2863.3 mA
RILIM = 11.5 KΩ 2525.4 2806 3086.6 mA
RILIM = 9.53 KΩ 3047.4 3386 3724.6 mA
RILIM = 0 Ω (short to GND) 3017.5 3550 4082.5 mA
RILIM = 11.5 KΩ, TJ  = 25℃ 2666 2806 2946 mA
IOS_OUT OUT output short-circuit current limit Short circuit current limit 390 450 495 mA
IOS_VCONN VCONN output short-circuit current limit Short circuit current limit 240 300 360 mA
CABLE COMPENSATION VOLTAGE
VDROP_COM Cable compensation voltage IPA_BUS or IPB_BUS = 2.4 A, VSET = GND (set 5.17-V output) 70 90 110 mV
CC CONNECT MANAGEMENT
ISRC_CC_3A Sourcing current CC pin voltage: 0 V ≤ VCCn ≤ 2.45 V  304 330 356 µA
ISRC_CC_1.5A Sourcing current in thermal management(Temp warm) CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V , TA > 85℃ 167 180 194 µA
ISRC_CC_DFLT Sourcing current in thermal management(Temp hot) CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V , TA > 85℃ 64 80 105 µA
IREV Reverse leakage current CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy floating, VEN_UV = 0 V or VSENSE, 0 V ≤ VIN ≤ 26 V  IREV is current into CCx pin   2.75 10 µA
VTH_R Rising threshold voltage for VCONN not discharged CC pin that was providing VCONN in previous SINK state 670 700 730 mV
VTH_HYS Hysteresis 100 mV
FAULT
VOL PA_FAULT, PB_FAULT Output low voltage ISNK_PIN = 1 mA 250 mV
IOFF PA_FAULT, PB_FAULT Off-state leakage VPIN = 5.5 V 2.2 µA
BC 1.2 DOWNSTREAM CHARGING PORT
RDPM_SHORT DP and DM shorting resistance 70 200 Ω
DIVIDER 3 MODE
VDP_DIV3 DP output voltage 2.57 2.7 2.84 V
VDM_DIV3 DM output voltage 2.57 2.7 2.84 V
RDP_DIV3 DP output impedance IDP_IN = –5 µA 24 30 36 kΩ
RDM_DIV3 DM output impedance IDM_IN = –5 µA 24 30 36 kΩ
1.2-V MODE
VDP_1.2V DP output voltage 1.12 1.2 1.26 V
VDM_1.2V DM output voltage 1.12 1.2 1.26 V
RDP_1.2V DP output impedance IDP_IN = –5 µA 84 100 126 kΩ
RDM_1.2V DM output impedance IDM_IN = –5 µA 84 100 126 kΩ
FREQ/SYNC THRESHOLD
VIH_FREQ/SYNC FREQ/SYNC high threshold for external clock synchronization Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin) 2 V
VIL_FREQ/SYNC FREQ/SYNC low threshold for external clock synchronization Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin) 0.8 V
TEMPERATURE SENSING
VWARN_HIGH Temperature warning threshold rising As percentage to VSENSE 0.475 0.5 0.525 V/V
VWARN_HYS Hysteresis As percentage to VSENSE 0.1 V/V
VHOT_HIGH Temperature Hot assert threshold rising to reduce SENS voltage As percentage to VSENSE 0.6175 0.65 0.6825 V/V
VHOT_HYS Hysteresis As percentage to VSENSE 0.1 V/V
VR_VSENS VSENSE voltage decay when Temperature Hot assert TS pin voltage rise above 0.65*VSENSE 4.77 V
THERMAL SHUTDOWN
TLS_SD USB Load Switch Over Temperature OTSD2&3 threshold 160 °C
Recovery threshold 150 °C
TSD Thermal shutdown Shutdown threshold 166 °C
Recovery threshold 154 °C