SLVSCU9B August   2015  – September 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GND
      2. 8.3.2 VIN
      3. 8.3.3 dV/dT
      4. 8.3.4 BFET
      5. 8.3.5 EN/UVLO
      6. 8.3.6 ILIM
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step by Step Design Procedure
          2. 9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 9.2.1.2.3 Undervoltage Lockout Set Point
          4. 9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
            2. 9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
          5. 9.2.1.2.5 Support Component Selection—CVIN
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
          2. 9.2.2.2.2 Undervoltage Lockout Set Point
          3. 9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Controlled Power Down using TPS25924x
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VIN Supply voltage(1) –0.3 20 V
VIN (10-ms transient) 22
OUT Output voltage –0.3 VIN + 0.3 V
OUT (transient < 1 µs) –1.2 V
ILIM Voltage –0.3 7 V
EN/UVLO –0.3 7
dV/dT –0.3 7
BFET –0.3 30
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Input voltage 4.5 12 13.8 V
BFET 0 VIN+6
dV/dT, EN/UVLO 0 6
ILIM 0 3
IOUT Continuous output current 0 5 A
ILIM Resistance 10 100 162 kΩ
OUT External capacitance 0.1 1 1000 µF
dV/dT 1 1000 nF
TJ Operating junction temperature –40 25 125 °C
TA Operating Ambient temperature –40 25 85 °C

7.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)(1)
THERMAL METRIC TPS25924x UNIT
DRC (VSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 45.9 °C/W
RθJCtop Junction-to-case (top) thermal resistance 53 °C/W
RθJB Junction-to-board thermal resistance 21.2 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 21.4 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 5.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN (INPUT SUPPLY)
VUVR UVLO threshold, rising 4.15 4.3 4.45 V
VUVhyst UVLO hysteresis(1) 5%
IQON Supply current Enabled: EN/UVLO = 2 V 0.3 0.42 0.55 mA
IQOFF EN/UVLO = 0 V 0.13 0.225 mA
VOVC Over-voltage clamp VIN > 16.5 V, IOUT = 10 mA 13.8 15 16.5 V
EN/UVLO (ENABLE/UVLO INPUT)
VENR EN threshold voltage, rising 1.37 1.4 1.44 V
VENF EN threshold voltage, falling 1.32 1.35 1.39 V
IEN EN Input leakage current 0 V ≤ VEN ≤ 5 V –100 0 100 nA
dV/dT (OUTPUT RAMP CONTROL)
IdVdT dV/dT charging current(1) VdVdT = 0 V 220 nA
RdVdT_disch dV/dT discharging resistance EN/UVLO = 0 V, IdVdT = 10 mA sinking 50 73 100 Ω
VdVdTmax dV/dT max capacitor voltage(1) 5.5 V
GAINdVdT dV/dT to OUT gain(1) ΔVdVdT 4.85 V/V
ILIM (CURRENT LIMIT PROGRAMMING)
IILIM ILIM bias current(1) 10 µA
IOL Overload current limit(2) RILIM = 10 kΩ, VVIN-OUT = 1 V 1.02 A
RILIM = 45.3 kΩ, VVIN-OUT = 1 V 1.79 2.10 2.42
RILIM = 100 kΩ, VVIN-OUT = 1 V 3.46 3.75 4.03
RILIM = 150 kΩ, VVIN-OUT = 1 V 4.5 5.1 5.7
IOL-R-Short RILIM = 0 Ω, shorted resistor current limit (single point failure test: UL60950)(1) 0.84 A
IOL-R-Open RILIM = OPEN, open resistor current limit (single point failure test: UL60950)(1) 0.73 A
ISCL Short-circuit current limit(2) RILIM = 10 kΩ, VVIN-OUT = 12 V 1 A
RILIM = 45.3 kΩ, VVIN-OUT = 12 V 1.66 1.98 2.37
RILIM = 100 kΩ, VVIN-OUT = 12 V 2.90 3.32 3.85
RILIM = 150 kΩ, VVIN-OUT = 12 V 3.7 4.5 5.5
RATIOFASTRIP Fast-trip comparator level w.r.t. overload current limit(1) IFASTRIP : IOL 160%
VOpenILIM ILIM open resistor detect threshold(1) VILIM rising, RILIM = OPEN 3.1 V
OUT (PASS FET OUTPUT)
RDS(on) FET ON resistance TJ = 25°C 21 28 37 mΩ
TJ = 125°C 39 48
IOUT-OFF-LKG OUT bias current in off state VEN/UVLO = 0 V, VOUT = 0 V (sourcing) –5 0 1.2 µA
IOUT-OFF-SINK VEN/UVLO = 0 V, VOUT = 300 mV (sinking) 10 15 20
BFET (BLOCKING FET GATE DRIVER)
IBFET BFET charging current(1) VBFET = VOUT 2 µA
VBFETmax BFET clamp voltage(1) VVIN + 6.4 V
RBFETdisch BFET discharging resistance to GND VEN/UVLO = 0 V, IBFET = 100 mA 15 26 36 Ω
TSD (THERMAL SHUT DOWN)
TSHDN TSD threshold, rising(1) 150 °C
TSHDNhyst TSD hysteresis(1) 10 °C
Thermal fault: latched or auto-retry TPS259240 Latched
TPS259241 Auto-retry
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(2) Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.

7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TON Turnon delay(1) EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at OUT 220 µs
tOFFdly Turnoff delay(1) EN/UVLO↓ to BFET↓, CBFET = 0 0.4 µs
dV/dT (OUTPUT RAMP CONTROL)
tdVdT Output ramp time EN/UVLO → H to OUT = 11.7 V, CdVdT = 0 0.7 1 1.3 ms
EN/UVLO → H to OUT = 11.7 V, CdVdT = 1 nF(1) 12
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly Fast-Trip comparator delay(1) IOUT > IFASTRIP to IOUT= 0 (Switch off) 300 ns
BFET (BLOCKING FET GATE DRIVER)
tBFET-ON BFET Turnon duration(1) EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF 4.2 ms
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF 42
tBFET-OFF BFET Turnoff duration(1) EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF 0.4 µs
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF 1.4
THERMAL SHUTDOWN (TSD)
tTSDdly Retry delay after TSD recovery, TJ < [TSHDN - 10°C](1) TPS259241 only 100 µs
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

7.7 Typical Characteristics

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
TPS259240 TPS259241 C001_SLVSC11.png
Figure 1. Input UVLO vs Temperature
TPS259240 TPS259241 C003_SLVSC11.png
Figure 3. IVIN-ON vs VIN
TPS259240 TPS259241 C026_SLVSC11.png
Figure 5. RDSON vs Temperature
TPS259240 TPS259241 C010_SLVSC11.png
Figure 7. IdVdT vs Temperature
TPS259240 TPS259241 C015_revB_SLVSC11.gif
Figure 9. VEN-VIH, VEN-VIL vs Temperature
TPS259240 TPS259241 D021_SLVSCU9.gif
RILIM = 0 Ω
Figure 11. IOL-R-Short vs Temperature
TPS259240 TPS259241 D001_SLVSCU9.gif
RILIM = 100 kΩ
Figure 13. IVOUT vs VVIN-OUT
TPS259240 TPS259241 D027_SLVSCU9.gif
RILIM = 150 kΩ
Figure 15. IVOUT vs VVIN-OUT
TPS259240 TPS259241 C031_SLVSC11_CU8.gif
RILIM = 100 kΩ
Figure 17. IOL, ISC vs Temperature
TPS259240 TPS259241 C035_SLVSC11.png
Figure 19. VOpenILIM vs Temperature
TPS259240 TPS259241 D004_SLVSC11.gif
Figure 21. Overload Current Limit vs RILIM Resistor
TPS259240 TPS259241 fig07_revB_SLVSC11.gif
Figure 23. Transient: Over-Voltage Clamp
TPS259240 TPS259241 fig18_revB2_lvsc11.gif
CdVdT = 1nF, COUT = 10 µF, ROUT = 5.7Ω
Figure 25. Transient: Output Ramp
TPS259240 TPS259241 fig022_revB_SLVSC11.gif
EN ↓
Figure 27. Turnoff Delay to BFET
TPS259240 TPS259241 fig38_revB2_lvsc11.gif
TPS259241
Figure 29. Transient: Recovery From Short Circuit / Over Current
TPS259240 TPS259241 fig40_revB2_lvsc11.gif
ILOAD Stepped From 50% to 120%, back to 50%
Figure 31. Transient: Overload Current Limit
TPS259240 TPS259241 Fig_25_slvscu9.png
RILIM = 150 kΩ
Figure 33. Short Circuit (Zoom): Fast-Trip Comparator
TPS259240 TPS259241 fig42_revB2_lvsc11.gif
TPS259240
Figure 35. Transient: Thermal Fault Latched
TPS259240 TPS259241 C002_SLVSC11.png
Figure 2. IQ-OFF vs VIN
TPS259240 TPS259241 C005_SLVSC11.png
Figure 4. VOVC vs Temperature Across IOUT
TPS259240 TPS259241 C009B_SLVSC11.png
Figure 6. TON vs Temperature
TPS259240 TPS259241 C013_SLVSC11.png
Figure 8. TdVdT vs CdVdT
TPS259240 TPS259241 D016_SLVSCU9.gif
Figure 10. IEN (Leakage Current) vs VEN
TPS259240 TPS259241 D022_SLVSCU9.gif
RILIM = OPEN
Figure 12. IOL-R-Open vs Temperature
TPS259240 TPS259241 D002_SLVSCU9.gif
RILIM = 45.3 kΩ
Figure 14. IVOUT vs VVIN-OUT
TPS259240 TPS259241 C030_SLVSC11_CU8.gif
RILIM = 150 kΩ
Figure 16. IOL, ISC vs Temperature
TPS259240 TPS259241 C032_SLVSC11_CU8.gif
RILIM = 45.3 kΩ
Figure 18. IOL, ISC vs Temperature
TPS259240 TPS259241 D031_SLVSCU9.gif
Figure 20. Accuracy vs Overload Current Limit
TPS259240 TPS259241 D037_SLVSCU9.gif
Figure 22. Thermal Shutdown Time vs Power Dissipation
TPS259240 TPS259241 fig17_revB2_lvsc11.gif
CdVdT = OPEN, COUT = 4.7 µF
Figure 24. Transient: Output Ramp
TPS259240 TPS259241 fig21_revB2_lvsc11.gif
EN ↓
Figure 26. Transient: Turnoff Delay
TPS259240 TPS259241 fig23_revB2_lvsc11.gif
VIN↓
Figure 28. Turnoff Delay to BFET
TPS259240 TPS259241 fig39_revB2_lvsc11.gif
TPS259241
Figure 30. Transient: Wake Up to Short Circuit
TPS259240 TPS259241 FP_24_35_slvscu9.png
RILIM = 150 kΩ
Figure 32. Transient: Output Short Circuit
TPS259240 TPS259241 Fig_29_slvscu9.png
TPS259241
Figure 34. Transient: Thermal Fault Auto-Retry