SLVSCQ3B August 2015 – June 2016
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPA25925x/6x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in controlling the in-rush current and provides precise current limiting during overload conditions for systems such as Set-Top-Box, DTVs, Gaming Consoles, SSDs, HDDs and Smart Meters. The device also provides robust protection for multiple faults on the sub-system rail.
The following can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder.
Table 1 lists the TPA25925x/6x design requirements.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage , VIN | 12 V |
Undervoltage lockout set point, V(UV) | Default: VUVR = 4.3 V |
Overvoltage protection set point , V(OV) | Default: VOVC = 15 V |
Load at start-up, RL(SU) | 4 Ω |
Current limit, IOL | 3.7 A |
Load capacitance, COUT | 1 µF |
Maximum ambient temperatures, TA | 85°C |
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
For ILIM = 3.7 A, from Equation 4, RILIM is 100 kΩ, choose closest standard value resistor with 1% tolerance.
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5.
Where VENR is enable voltage rising threshold (1.4 V). Because R1 and R2 leak the current from input supply (Vin), these resistors must be selected based on the acceptable leakage current from input power supply (Vin).
The current drawn by R1 and R2 from the power supply {I(R12) = V(IN)/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R12) must be chosen to be 20x greater than the leakage current expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Because EN/UVLO pin is rated only to 7 V, it cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, VUVR. This is calculated using Equation 6.
Where VUVR is 4.3 V, Power fail threshold set is : 4.1 V.
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases.
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across the internal FET decreases. The average power dissipated in the device during start-up is calculated using Equation 8.
For TPS25926x device, the inrush current is determined as shown in Equation 7.
Power dissipation during start-up is:
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
When load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during TdVdT time. Equation 9 to Equation 12 show the average power dissipation in the internal FET during charging time due to resistive load.
Total power dissipated in the device during startup is:
Total current during startup is given by:
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by:
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 43.
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2.
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 14.
The inrush power dissipation is calculated using Equation 15.
For 90 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 43 at TA = 85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any load on output.
Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is calculated using Equation 9.
The total device power dissipation during start up is given in Equation 17.
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 6.09 W is more than 10 ms. So it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 4 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of CdVdT capacitor.
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.
TPS25926x |
TPS25926x |