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The TPS25940 eFuse Power Switch is a compact, feature rich power management device with a full suite of protection functions, including a low power DevSleep™ mode that supports compliance with the SATA™ Device Sleep standard. The wide operating range allows control of many popular DC bus voltages. Integrated back to back FETs provide bidirectional current control making the device well suited for systems with load side holdup energy that must not drain back to a failed supply bus.
Load, source and device protection are provided with many programmable features including overcurrent, dVo/dt ramp and overvoltage, undervoltage thresholds. For system status monitoring and downstream load control, the device provides PGOOD, FLT and precise current monitor output. Precise programmable undervoltage, overvoltage thresholds and the low IQ DevSleep mode simplify SSD power management design.
The TPS25940 monitors V(IN) and V(OUT) to provide true reverse current blocking when V(IN) < (V(OUT) - 10 mV). This function supports swift changeover to a boosted voltage energy storage element in systems where backup voltage is greater than bus voltage.
PART NUMBER(2) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS25940A | WQFN (20) | 3.00 mm x 4.00 mm |
TPS25940L |
Changes from * Revision (June 2014) to A Revision
NAME | NO. | I/O | DESCRIPTION |
---|---|---|---|
DEVSLP | 1 | I | Active High. DevSleep Mode control. A high at this pin will activate the DevSleep mode(Low Power Mode). |
PGOOD | 2 | O | Active High. A high indicates PGTH has crossed the threshold value. It is an open drain output. |
PGTH | 3 | I | Positive input of PGOOD comparator. |
OUT | 4 - 8 | O | Power Output of the device. |
IN | 9 - 13 | I | Power Input and supply voltage of the device. |
EN/UVLO | 14 | I | Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert FLT to indicate power-failure. When pulled to GND, resets the fault latch in TPS25940L. |
OVP | 15 | I | Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and assert FLT to indicate overvoltage. |
GND | 16 | — | Ground. |
ILIM | 17 | I/O | A resistor from this pin to GND sets the overload and short-circuit current limit. |
dVdT | 18 | I/O | A capacitor from this pin to GND sets the ramp rate of output voltage. |
IMON | 19 | O | This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage, used as analog current monitor. |
FLT | 20 | O | Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, Reverse voltage and Thermal shutdown event. It is an open drain output. |
PowerPADTM | The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be connected to a PCB ground plane using multiple vias for good thermal performance. |