TPS25940x 2.7 – 18V eFuse with True Reverse Blocking and DevSleep Support for SSDs

1 Features

• 2.7 V – 18 V Operating Voltage, 20 V (Max)
• 42 mΩ R_ON (Typical)
• 0.6 A to 5.3 A Adjustable Current Limit (±8%)
• IMON Current Indicator Output (±8%)
• 200 μA Operating I_Q (Typical)
• 95 μA DevSleep Mode I_Q (Typical)
• 15 μA Disabled I_Q (Typical)
• ±2% Overvoltage, Undervoltage Threshold
• Reverse Current Blocking
• 1 μs Reverse Voltage Shutoff
• Programmable dV_o/dt Control
• Power Good and Fault Outputs
• -40°C to 125°C Junction Temperature Range
• UL 2367 Recognized
  • File No. 169910
  • R_ILIM ≥ 20 kΩ (4.81 A max)
• UL60950 - Safe during Single Point Failure Test
  • Open/Short ILIM detection

2 Applications

• PCIe/SATA/SAS HDD and SSD Drives
• Enterprise and Micro Servers
• Smart Load Switch
• Set-Top-Box (STB), DTVs and Game Consoles
• RAID Cards - Holdup Power Management
• Telecom Switches and Routers
• Adapter Powered Devices

3 Description

The TPS25940 eFuse Power Switch is a compact, feature rich power management device with a full suite of protection functions, including a low power DevSleep™ mode that supports compliance with the SATA™ Device Sleep standard. The wide operating range allows control of many popular DC bus voltages. Integrated back to back FETs provide bidirectional current control making the device well suited for systems with load side holdup energy that must not drain back to a failed supply bus.

Load, source and device protection are provided with many programmable features including overcurrent, dV_o/dt ramp and overvoltage, undervoltage thresholds. For system status monitoring and downstream load control, the device provides PGOOD, FLT and precise current monitor output. Precise programmable undervoltage, overvoltage thresholds and the low I_Q DevSleep mode simplify SSD power management design.

The TPS25940 monitors V_(IN) and V_(OUT) to provide true reverse current blocking when V_(IN) < (V_(OUT) - 10 mV). This function supports swift changeover to a boosted voltage energy storage element in systems where backup voltage is greater than bus voltage.

1. For all available packages, see the orderable addendum at the end of the datasheet.
2. TPS25940L = Latched, TPS25940A = Auto Retry

4 Simplified Schematic

Power Fail Detection and Blocking

5 Revision History

Changes from * Revision (June 2014) to A Revision

• Changed Features From: UL2367 Recognition Pending To: UL 2367 Recognized, R_ILIM ≥ 20 kΩ (4.81 A max), File No. 169910Go
• Moved the Storage Temperature From the Handling Ratings table To Absolute Maximum Ratings table Go
• Changed the Handling Ratings table To: ESD Ratings table Go
• Added Test Condition to I_(LIM): "R_(ILIM) = 20 kΩ" in the Electrical CharacteristicsGo
• Changed Figure 24.Go
• Added condition R_(ILIM) = 17.8 kΩ to Figure 40 and Figure 41Go
• Changed Figure 43Go
• Changed Equation 6 to include I_{(IMON_OS)}Go
• Added the NOTE to Application and ImplementationGo
• Added Note to Figure 57Go
• Changed Equation 35 From: V_(IN) x I_(LOAD) To: V_(IN) + I_(LOAD)Go

6 Pin Configuration and Functions

TPS25940

RVC PACKAGE

(TOP VIEW)

7 Specifications

7.7 Typical Characteristics

Conditions are –40°C ≤ T_A = T_J ≤ 125°C, V_(IN) = 12 V, V_(EN/UVLO) = 2 V, V_(OVP) = V_(DEVSLP) = V_(PGTH) = 0 V, R_(ILIM) = 150 kΩ, C_(OUT) = 1 µF, C_(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)

Figure 1. UVLO Threshold Voltage vs Temperature

Figure 3. Input Supply Current vs Supply Voltage at Shutdown

Figure 5. EN Threshold Voltage vs Temperature

Figure 7. PGTH Threshold Voltage vs Temperature

Figure 9. Enable Turn ON Delay vs Temperature

Figure 11. OVP Disable Delay vs Temperature

Figure 13. DEVSLP Pull Down Current vs Temperature

Figure 15. Output Ramp Time vs C_(dVdT)

Figure 17. Current Limit Accuracy vs Current Limit

Figure 19. Current Limit (% Normalized) vs R_(LIMIT) Resistor

Figure 21. Current Limit for R_(ILIM) = Open and Short vs Temperature

Figure 23. Fast Trip Threshold vs Current Limit

Figure 25. GAIN_(IMON) vs Temperature

Figure 27. R_ON vs Temperature Across Load Current

Figure 29. V_(REVTH) vs Temperature

Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom)

Figure 31. Thermal Shutdown Time vs Power Dissipation

V(IN) = 11 V

Figure 33. Turn ON and OFF with Enable

R(FLT)=100 kΩ

Figure 35. EN Turn OFF Delay : EN ↓ to Fault ↓

V(IN) = 12 V	RL = 12 Ω	R(FLT)=100 kΩ

Figure 37. OVP Turn ON delay: OVP ↓ to Output Ramp ↑

V(IN) = 12 V	RL = 12 Ω	R(FLT)= 100 kΩ
		R(PGOOD)= 100 kΩ

Figure 39. Power Good Delay (Falling)

R(FLT)= 100 kΩ	R(IMON) = 16.9 kΩ	R(ILIM) = 17.8 kΩ

Figure 41. Hot-Short: Fast Trip Response (Zoomed)

Figure 2. Input Supply Current vs Supply Voltage During Normal Operation

Figure 4. Input Supply Current vs Supply Voltage in DevSleep Mode

Figure 6. OVP Threshold Voltage vs Temperature

Figure 8. EN Threshold Voltage for Low IQ mode vs Temperature

Figure 10. Enable Turn OFF Delay vs Temperature

Figure 12. DEVSLP Threshold Voltage vs Temperature

Figure 14. GAIN_(dVdT) vs Temperature

Figure 16. Current Limit vs Current Limit Resistor

Figure 18. Current Limit vs Temperature Across R_(ILIM)

Thermal shutdown occurs when I(LIM) = 5.3 A
and [V(IN) - V(OUT)] > 8 V

Figure 20. Current Limit Normalized (%) vs V_(IN) - V_(OUT)

Figure 22. Current Limit in DevSleep Mode vs Temperature

Figure 24. IMON Offset vs Temperature

Figure 26. Current Monitor Output vs Output Current

Figure 28. OUT Leakage Current in Off State vs Temperature

Figure 30. V_(FWDTH) vs Temperature

V(IN) = 4.5 V

Figure 32. Turn ON with Enable

R(FLT)=100 kΩ

Figure 34. EN Turn ON Delay : EN ↑ to Output Ramp ↑

V(IN) = 12 V

RL = 12 Ω

R(FLT)=100 kΩ

Figure 36. OVP Turn OFF delay: OVP ↑ to Fault ↓

V(IN) = 12 V	RL = 12 Ω	R(FLT)= 100 kΩ
		R(PGOOD)= 100 kΩ

Figure 38. Power Good Delay (Rising)

R(FLT) = 100 kΩ	R(IMON) = 16.9 kΩ	R(ILIM) = 17.8 kΩ

Figure 40. Hot-Short: Fast Trip Response and Current Regulation

8 Parametric Measurement Information

Figure 42. Timing Diagrams