SLVSHR9 Data sheet

SLVSHR9 December 2024 TPS25984B

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RZJ|32
- MPQF664A

サーマルパッド・メカニカル・データ

RZJ|32
- QFND783

発注情報

8.2.3 Detailed Design Procedure

Determining the number of eFuse devices to be used in parallel
By factoring in a small variation in the junction to ambient thermal resistance (R_θJA), a single TPS25984Bx eFuse is rated at a maximum steady state DC current of 55A at an ambient temperature of 70°C. Therefore, Equation 18 can be used to calculate the number of devices (N) to be in parallel to support the maximum steady state DC load current (I_LOAD(max)), for which the solution must be designed.
Equation 18. $N \geq \frac{I_{O U T (m a x)} (A)}{55 A}$
According to Table 8-1, I_OUT(max) is 275A. Therefore, six (6) TPS25984Bx eFuses are connected in parallel.

Selecting the C_DVDT capacitor to control the output slew rate and start-up time

For a robust design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of magnitude greater than static stresses, so it is crucial to establish the right start-up time and inrush current limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up.

Table 8-2 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence of different loads during start-up if the power good (PG) signal is not used to turn on all the downstream loads.

Table 8-2 Calculation of Average Power Loss During Inrush

Type of Loads During Start-Up	Expressions to Calculate the Average Inrush Power Loss
Only output capacitor of C_LOAD (µF)	Equation 19. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}}$
Output capacitor of C_LOAD (µF) and constant resistance of R_{LOAD(Startup)} (Ω) with turn-ON threshold of V_RTH (V)	Equation 20. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + \frac{V_{I N}^{2}}{R_{L O A D (S t a r t u p)}} [\frac{1}{6} - \{\frac{1}{2} {(\frac{V_{R T H}}{V_{I N}})}^{2}\} + \{\frac{1}{3} {(\frac{V_{R T H}}{V_{I N}})}^{3}\}]$
Output capacitor of C_LOAD (µF) and constant current of I_{LOAD(Startup)} (A) with turn-ON threshold of V_CTH (V)	Equation 21. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + V_{I N} I_{L O A D (S t a r t u p)} [\frac{1}{2} - (\frac{V_{C T H}}{V_{I N}}) + \{\frac{1}{2} {(\frac{V_{C T H}}{V_{I N}})}^{2}\}]$
Output capacitor of C_LOAD (µF) and constant power of P_{LOAD(Startup)} (W) with turn-ON threshold of V_PTH (V)	Equation 22. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + P_{L O A D (S t a r t u p)} [\ln (\frac{V_{P T H}}{V_{I N}}) + (\frac{V_{P T H}}{V_{I N}}) - 1]$

Where V_IN is the input voltage and T_ss is the start-up time.

With the different combinations of loads during start-up, the total average inrush power loss (P_INRUSH) can be calculated using the formulas described in Table 8-2. For a successful start-up, the system must satisfy the condition stated in Equation 23.

Equation 23.

P_{I N R U S H} (W) \sqrt{T_{s s} (s)} < 10 \times N

Where N denotes the number of eFuses in parallel and 10W√s is the SOA limit of a single TPS25984Bx eFuse. This equation can be used to obtain the maximum allowed T_ss.

Note:

TI recommends to use a T_ss in the range of 5ms to 120ms to prevent start-up issues.

A capacitor (C_DVDT) must be added at the DVDT pin to GND to set the required value of T_ss as calculated above. The following equations are used to compute the value of C_DVDT. The DVDT pins of all the eFuses in a parallel chain must be connected together.

For B0/1/3 variants:

Equation 24.

C_{D V D T} (p F) = \frac{51300 \times N}{S R (V / m s)}

For B2 variant:

Equation 25.

C_{D V D T} (p F) = \frac{135000 \times N}{S R (V / m s)}

In this design example, C_LOAD = 40mF, R_{LOAD(Startup)} = 0.48Ω, V_RTH = 0V, V_IN = 12V, and T_ss = 10ms. P_INRUSH is calculated to be 340W using the equations provided in the Table 8-2. It can be verified that the system satisfies condition stated in Equation 23 and therefore capable of a successful start-up. If Equation 23 does not hold true, start-up loads or T_ss must be tuned to prevent chances of thermal shutdown during start-up. Using V_IN = 12V, T_ss = 10ms, the required C_DVDT value can be calculated to be 258nF. The closest standard value of C_DVDT is 250nF with 10% tolerance and DC voltage rating of 25V.

Note:

In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-on threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action ensures that the load is turned on only when the eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal shutdown.

Selecting the R_IREF resistor to set the reference voltage for overcurrent protection
In this parallel configuration, the IREF internal current source (I_IREF) of all the eFuse interacts with the external IREF pin resistor (R_IREF) to generate the reference voltage (V_IREF) for the overcurrent protection blocks. When the voltage at the IMON pin (V_IMON) is used as an input to an ADC to monitor the system current or to implement the Platform Power Control ( Intel® PSYS) functionality inside the VR controller, V_IREF must be set to half of the maximum voltage range of the ISYS_IN input of the controller. This action provides the necessary headroom and dynamic range for the system to accurately monitor the load current up to the fast-trip threshold (2 × I_OCP). Equation 26 is used to calculate the value of R_IREF.
Equation 26. $V_{I R E F} = I_{I R E F} \times R_{I R E F} \times N$
In this design example, V_IREF is set at 1.62V. With I_IREF = 10µA (typical), we can calculate the target R_IREF to be 27kΩ. The closest standard value of R_IREF is 27kΩ with 0.1% tolerance and power rating of 100mW. For improved noise immunity, place a 1000pF ceramic capacitor from the IREF pin to GND. The IREF pins of all the eFuses in a parallel chain must be connected together.
Note:
Maintain V_IREF within the recommended voltage to ensure proper operation of overcurrent detection circuit.

Selecting the R_IMON resistor to monitor current through each eFuse
TPS25984Bx eFuse continuously monitors the current flowing through it (I_DEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces a proportional voltage (VILIM) across the respective ILIM pin resistor (R_IMON), which is expressed as:

Equation 27. $V_{I M O N} = I_{O U T} \times G_{I M O N} \times N \times R_{I M O N}$

G_IMON is the current monitor gain (I_IMON : I_OUT), whose typical value is 10µA/A
Selecting the R_ILIM resistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during steady state and inrush current during startup

TPS25984Bx eFuse responds to the output overcurrent conditions during steady-state by turning off the output after a fixed transient fault blanking interval. This eFuse continuously senses the total system current (I_OUT) and produces a proportional analog current output (I_ILIM) on the ILIM pin. This generates a voltage (V_ILIM) across the ILIM pin resistor (R_ILIM) in response to the load current, which is defined as Equation 27.

Equation 28. $V_{I L I M} = I_{O U T} \times G_{I L I M} \times R_{I L I M}$

G_ILIM is the current monitor gain (I_ILIM : I_OUT), whose typical value is 7.5µA/A. The overcurrent condition is detected by comparing the V_ILIM against the V_IREF as a threshold. The circuit-breaker threshold during steady-state (I_OCP) can be calculated using Equation 29.

Equation 29. $I_{O C P} = \frac{{0.75 × V}_{I R E F}}{G_{I L I M} \times R_{I L I M}}$

In this design example, I_OCP is set at 480A, and R_ILIM can be calculated to be 2kΩ with G_ILIM as 7.5 µA/A and V_IREF as 1.62V. The nearest value of R_ILIM is 2kΩ with 0.1% tolerance and power rating of 100 mW.

Overcurrent limit during start-up: During inrush, the overcurrent condition for each device is detected by comparing its own load current information (V_ILIM) with a scaled reference voltage as depicted in Equation 30.

Equation 30. ${C L R E F}_{S A T} = 0.4 \times V_{I R E F}$

The current limit threshold during start-up can be calculated using Equation 31.

Equation 31. $I_{I L I M (S t a r t u p)} = \frac{{C L R E F}_{S A T}}{G_{I L I M} \times R_{I L I M}}$

By using a R_ILIM value of 2kΩ for each device, the start-up current is limited to around 43A for each device.

Selecting the resistors to set the undervoltage lockout threshold
The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of R₁ and R₂ connected between IN, EN/UVLO, and GND pins of the device as described in Section 7.3.1. The resistor values required for setting up the UVLO threshold are calculated using Equation 32.
Equation 32. $V_{I N (U V)} = V_{U V L O (R)} \frac{R_{1} + R_{2}}{R_{2}}$
To minimize the input current drawn from the power supply, TI recommends using higher resistance values for R₁ and R₂. The current drawn by R₁ and R₂ from the power supply is I_R12 = V_IN / (R₁ + R₂). However, the leakage currents due to external active components connected to the resistor string can add errors to these calculations. So, the resistor string current, I_R12 must be 20 times greater than the leakage current at the EN/UVLO pin (I_ENLKG). From the device electrical specifications, I_ENLKG is 0.1µA (maximum) and UVLO rising threshold V_UVLO(R) = 1.52V (max). From the design requirements, V_INUVLO = 10.8 V. First choose the value of R₁ = 1MΩ and use Equation 13 to calculate R₂ >163.79 kΩ. Use the closest standard 1 % resistor values: R₁ = 1MΩ and R₂ = 165kΩ. For noise reduction, place a 1000pF ceramic capacitor across the EN/UVLO pin and GND.

Selecting the pullup resistors and power supplies for PG and GOK/FLT pins
GOK/FLT and PG are open-drain outputs. If these logic signals are used, the corresponding pins must be pulled up to the appropriate voltages (< 5V) through 10kΩ pullup resistances.
Note:
GOK/FLT pin must be pulled up to a voltage in the range of 2.5V to 5V through a 100kΩ resistance.

Selection of TVS diode at input and Schottky diode at output
In the case of a short circuit and overload current limit when the device interrupts a large amount of current instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes (transients) are dependent on the value of inductance in series with the input or output of the device. Such transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for addressing this issue include:
1. Minimize lead length and inductance into and out of the device.
2. Use a large PCB GND plane.
3. Addition of the transient voltage suppressor (TVS) diodes to clamp the positive transient spike at the input.
4. Using Schottky diodes across the output to absorb negative spikes.
Refer to TVS Clamping in Hot-Swap Circuits and Selecting TVS Diodes in Hot-Swap and ORing Applications for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20V). These TVS diodes also help to limit the transient voltage at the IN pin during the hot-plug event. Four (4) SMDJ12A are used in parallel in this design example.
Note:
Maximum clamping voltage V_C specification of the selected TVS diode at I_pp (10/1000 μs) (V) must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of the eFuse.
Selection of the Schottky diodes must be based on the following criteria:
- The non-repetitive peak forward surge current (I_FSM) of the selected diode must be more than the fast-trip threshold (2 × I_OCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky diode is unable to meet the required I_FSM rating. Equation 33 calculates the number of Schottky diodes (N_Schottky) that must be in parallel.
  Equation 33. $N_{S c h o t t k y} > \frac{2 \times I_{O C P (T O T A L)}}{I_{F S M}}$
- Forward Voltage Drop (V_F) at near to I_FSM must be as small as possible. Ideally, the negative transient voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–1V).
- DC Blocking Voltage (V_RM) must be more than the maximum input operating voltage.
- Leakage current (I_R) must be as small as possible.
Three (3) SBR10U45SP5 are used in parallel in this design example.

Selecting C_IN and C_OUT
TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The value of C_IN must be kept small to minimize the current spike during hot-plug events. For each device, 0.1µF of C_IN is a reasonable target. Because C_OUT does not get charged during hot-plug, a larger value such as 2.2µF can be used at the OUT pin of each device.