JAJSMF5 データシート

JAJSMF5B september 2022 – june 2023 TPS25990

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RQP|26
- MPQF569A

サーマルパッド・メカニカル・データ

発注情報

8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)

The TPS25990 responds to output overcurrent conditions during steady-state by performing a circuit-breaker action after a user-adjustable transient fault blanking interval. This action allows the device to support a higher peak current for a short user-defined interval but also ensures robust protection in case of persistent output faults.

The device constantly senses the output load current and provides an analog current output (I_IMON) on the IMON pin which is proportional to the load current, which in turn produces a proportional voltage (V_IMON) across the IMON pin resistor (R_IMON) as per Equation 4.

Equation 4.

V_{I M O N} = I_{O U T} \times G_{I M O N} \times R_{I M O N}

Where G_IMON is the current monitor gain (I_IMON : I_OUT)

The overcurrent condition is detected by comparing this voltage against the voltage on the IREF pin as a reference. The reference voltage (V_IREF) can be controlled in two ways, which sets the overcurrent protection threshold (I_OCP) accordingly.

The reference voltage (V_IREF) can be generated using internal DAC and can be changed by programming the non-volatile configuration memory or dynamically through PMBus® writes to the VIREF register.
It is also possible to drive the IREF pin from an external low impedance precision reference voltage source.

The overcurrent protection threshold during steady-state (I_OCP) can be calculated using Equation 5.

Equation 5.

I_{O C P} = \frac{V_{I R E F}}{G_{I M O N} \times R_{I M O N}}

Note:

TI recommends to add a 1 nF capacitor from IREF pin to GND for improved noise immunity.

After an overcurrent condition is detected, that is the load current exceeds the programmed current limit threshold (I_OCP), but stays lower than the short-circuit threshold (I_SCP), the device starts running the internal overcurrent blanking digital timer (OC_TIMER). If the load current drops below the current limit threshold before the OC_TIMER expires, the circuit-breaker action is not engaged. This action allows short overload transient pulses to pass through the device without tripping the circuit. At the same time, the OC_TIMER is reset so that it is at its default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every overcurrent event.

If the overcurrent condition persists, the OC_TIMER continues to run and after it expires, the circuit-breaker action turns off the FET immediately.

Equation 23 can be used to calculate the R_IMON value for the desired overcurrent threshold.

Equation 6.

R_{I M O N} = \frac{V_{I R E F}}{G_{I M O N} \times I_{O C P}}

The duration for which transients are allowed can be programmed using OC_TIMER register setting through PMBus® writes.

Figure 8-4 illustrates the overcurrent response for TPS25990 eFuse. After the part shuts down due to a circuit-breaker fault, it either stays latched off or restarts automatically based on the RETRY_CONFIG register setting.

Figure 8-4 Steady-state Overcurrent (Circuit-Breaker) Response

When a transient overcurrent condition (the load current exceeds the programmed current limit threshold but the OC_TIMER does not expire) is detected, the device:

sets the OC_DET bit in the STATUS_MFR_SPECIFIC_2 register
fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as OC_DET and relative time stamp information
increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the Blackbox RAM registers is available to write.

Note:

It is assumed that the VIN_UV_WARN , VIN_OV_WARN, and VOUT_UV_WARN events are not triggered because of a step load transient.

When a persistent overcurrent condition (the load current exceeds the programmed current limit threshold and the OC_TIMER expires) is detected, the device:

sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register
sets the OUT_STATUS, INPUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD register
sets the VOUT_UV_WARN bit in the STATUS_OUT register
sets the OC_FLT bit in the STATUS_INPUT register
sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register
notifies the host by asserting SMBA, if it is not masked setting the STATUS_IN, PGOODB, and STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA Output in the GPIO_CONFIG_34 register
deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the GPIO_CONFIG_12 register
asserts the FLT signal, if it is not masked setting the OC_FLT bit high in the FAULT_MASK register and the GPIO2 pin is configured as FLT Output in the GPIO_CONFIG_12 register

Note:

It is assumed that the VIN_UV_WARN and VIN_OV_WARN events are not triggered because of a step load transient.