JAJSMF5B september   2022  – june 2023 TPS25990

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Logic Interface DC Characteristics
    7. 7.7  Telemetry
    8. 7.8  PMBus Interface Timing Characteristics
    9. 7.9  External EEPROM Interface Timing Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Switching Characteristics
    12. 7.12 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Timeout
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Single Point Failure Mitigation
        1. 8.3.5.1 IMON Pin Single Point Failure
        2. 8.3.5.2 ILIM Pin Single Point Failure
        3. 8.3.5.3 IREF Pin Single Point Failure
      6. 8.3.6  Analog Load Current Monitor (IMON)
      7. 8.3.7  Overtemperature Protection
      8. 8.3.8  Analog Junction Temperature Monitor (TEMP)
      9. 8.3.9  FET Health Monitoring
      10. 8.3.10 General Purpose Digital Input/Output Pins
        1. 8.3.10.1 Fault Response and Indication (FLT)
        2. 8.3.10.2 Power Good Indication (PG)
        3. 8.3.10.3 Parallel Device Synchronization (SWEN)
      11. 8.3.11 Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.11.1 Current Balancing During Start-Up
      12. 8.3.12 General Purpose Comparators
      13. 8.3.13 Output Discharge
      14. 8.3.14 PMBus® Digital Interface
        1. 8.3.14.1  PMBus® Device Addressing
        2. 8.3.14.2  SMBus Protocol
        3. 8.3.14.3  SMBus™ Message Formats
        4. 8.3.14.4  Packet Error Checking
        5. 8.3.14.5  Group Commands
        6. 8.3.14.6  SMBus™ Alert Response Address (ARA)
        7. 8.3.14.7  PMBus® Commands
          1. 8.3.14.7.1 Detailed Descriptions of PMBus® Commands
            1. 8.3.14.7.1.1  OPERATION (01h, Read/Write Byte)
            2. 8.3.14.7.1.2  CLEAR_FAULTS (03h, Send Byte)
            3. 8.3.14.7.1.3  RESTORE_FACTORY_DEFAULTS (12h, Send Byte)
            4. 8.3.14.7.1.4  STORE_USER_ALL (15h, Send Byte)
            5. 8.3.14.7.1.5  RESTORE_USER_ALL (16h, Send Byte)
            6. 8.3.14.7.1.6  BB_ERASE (F5h, Send Byte)
            7. 8.3.14.7.1.7  FETCH_BB_EEPROM (F6h, Send Byte)
            8. 8.3.14.7.1.8  POWER_CYCLE (D9h, Send Byte)
            9. 8.3.14.7.1.9  MFR_WRITE_PROTECT (F8h, Read/Write Byte)
            10. 8.3.14.7.1.10 CAPABILITY (19h, Read Byte)
            11. 8.3.14.7.1.11 STATUS_BYTE (78h, Read Byte)
            12. 8.3.14.7.1.12 STATUS_WORD (79h, Read Word)
            13. 8.3.14.7.1.13 STATUS_OUT (7Ah, Read Byte)
            14. 8.3.14.7.1.14 STATUS_IOUT (7Bh, Read Byte)
            15. 8.3.14.7.1.15 STATUS_INPUT (7Ch, Read Byte)
            16. 8.3.14.7.1.16 STATUS_TEMP (7Dh, Read Byte)
            17. 8.3.14.7.1.17 STATUS_CML (7Eh, Read Byte)
            18. 8.3.14.7.1.18 STATUS_MFR_SPECIFIC (80h, Read Byte)
            19. 8.3.14.7.1.19 STATUS_MFR_SPECIFIC_2 (F3h, Read Word)
            20. 8.3.14.7.1.20 PMBUS_REVISION (98h, Read Byte)
            21. 8.3.14.7.1.21 MFR_ID (99h, Block Read)
            22. 8.3.14.7.1.22 MFR_MODEL (9Ah, Block Read)
            23. 8.3.14.7.1.23 MFR_REVISION (9Bh, Block Read)
            24. 8.3.14.7.1.24 READ_VIN (88h, Read Word)
            25. 8.3.14.7.1.25 READ_VOUT (8Bh, Read Word)
            26. 8.3.14.7.1.26 READ_IIN (89h, Read Word)
            27. 8.3.14.7.1.27 READ_TEMPERATURE_1 (8Dh, Read Word)
            28. 8.3.14.7.1.28 READ_VAUX (D0h, Read Word)
            29. 8.3.14.7.1.29 READ_PIN (97h, Read Word)
            30. 8.3.14.7.1.30 READ_EIN (86h, Block Read)
            31. 8.3.14.7.1.31 READ_VIN_AVG (DCh, Read Word)
            32. 8.3.14.7.1.32 READ_VIN_MIN (D1h, Read Word)
            33. 8.3.14.7.1.33 READ_VIN_PEAK (D2h, Read Word)
            34. 8.3.14.7.1.34 READ_VOUT_AVG (DDh, Read Word)
            35. 8.3.14.7.1.35 READ_VOUT_MIN (DAh, Read Word)
            36. 8.3.14.7.1.36 READ_IIN_AVG (DEh, Read Word)
            37. 8.3.14.7.1.37 READ_IIN_PEAK (D4h, Read Word)
            38. 8.3.14.7.1.38 READ_TEMP_AVG (D6h, Read Word)
            39. 8.3.14.7.1.39 READ_TEMP_PEAK (D7h, Read Word)
            40. 8.3.14.7.1.40 READ_PIN_AVG (DFh, Read Word)
            41. 8.3.14.7.1.41 READ_PIN_PEAK (D5h, Read Word)
            42. 8.3.14.7.1.42 READ_SAMPLE_BUF (D8h, Block Read)
            43. 8.3.14.7.1.43 READ_BB_RAM (FDh, Block Read)
            44. 8.3.14.7.1.44 READ_BB_EEPROM (F4h, Block Read)
            45. 8.3.14.7.1.45 BB_TIMER (FAh, Read Byte)
            46. 8.3.14.7.1.46 PMBUS_ADDR (FBh, Read/Write Byte)
            47. 8.3.14.7.1.47 VIN_UV_WARN (58h, Read/Write Word)
            48. 8.3.14.7.1.48 VIN_UV_FLT (59h, Read/Write Word)
            49. 8.3.14.7.1.49 VIN_OV_WARN (57h, Read/Write Word)
            50. 8.3.14.7.1.50 VIN_OV_FLT (55h, Read/Write Word)
            51. 8.3.14.7.1.51 VOUT_UV_WARN (43h, Read/Write Word)
            52. 8.3.14.7.1.52 VOUT_PGTH (5Fh, Read/Write Word)
            53. 8.3.14.7.1.53 OT_WARN (51h, Read/Write Word)
            54. 8.3.14.7.1.54 OT_FLT (4Fh, Read/Write Word)
            55. 8.3.14.7.1.55 PIN_OP_WARN (6Bh, Read/Write Word)
            56. 8.3.14.7.1.56 IIN_OC_WARN (5Dh, Read/Write Word)
            57. 8.3.14.7.1.57 VIREF (E0h, Read/Write Byte)
            58. 8.3.14.7.1.58 GPIO_CONFIG_12 (E1h, Read/Write Byte)
            59. 8.3.14.7.1.59 GPIO_CONFIG_34 (E2h, Read/Write Byte)
            60. 8.3.14.7.1.60 ALERT_MASK (DBh, Read/Write Word)
            61. 8.3.14.7.1.61 FAULT_MASK (E3h, Read/Write Word)
            62. 8.3.14.7.1.62 DEVICE_CONFIG (E4h, Read/Write Word)
            63. 8.3.14.7.1.63 BB_CONFIG (E5h, Read/Write Byte)
            64. 8.3.14.7.1.64 OC_TIMER (E6h, Read/Write Byte)
            65. 8.3.14.7.1.65 RETRY_CONFIG (E7h, Read/Write Byte)
            66. 8.3.14.7.1.66 ADC_CONFIG_1 (E8h, Read/Write Byte)
            67. 8.3.14.7.1.67 ADC_CONFIG_2 (E9h, Read/Write Byte)
            68. 8.3.14.7.1.68 PK_MIN_AVG (EAh, Read/Write Byte)
            69. 8.3.14.7.1.69 VCMPxREF (EBh, Read/Write Byte)
            70. 8.3.14.7.1.70 PSU_VOLTAGE (ECh, Read/Write Byte)
            71. 8.3.14.7.1.71 CABLE_DROP (EDh, Read/Write Byte)
            72. 8.3.14.7.1.72 GPDAC1 (F0h, Read/Write Byte)
            73. 8.3.14.7.1.73 GPDAC2 (F1h, Read/Write Byte)
            74. 8.3.14.7.1.74 INS_DLY (F9h, Read/Write Byte)
        8. 8.3.14.8  Analog-to-digital Converter
        9. 8.3.14.9  Digital-to-analog Converters
        10. 8.3.14.10 DIRECT format Conversion
        11. 8.3.14.11 Blackbox Fault Recording
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
      3. 9.1.3 Multiple Devices, Independent Operation (Multi-zone)
    2. 9.2 Typical Application: 12-V, 4-kW Power Path Protection with PMBus® Interface in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.3.14.7.1.4 STORE_USER_ALL (15h, Send Byte)

STORE_USER_ALL is a standard PMBus® command that writes the contents of the certain Configuration RAM registers to their respective non-volatile configuration memory (NVM) or EEPROM locations. The TPS25990 has two (2) one-time programmable banks in the NVM which are available to the users to store their custom configurations. This command will try to write to NVM Bank-1 first if it’s not programmed yet. If NVM Bank-1 is already programmed, it will attempt to write to NVM Bank-2 if it’s not programmed. If NVM Bank-2 is already programmed, it will attempt to write to Page-2 of an external EEPROM if available and configured.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is write only.

Note:

  • This command should be preceded by the MFR_WRITE_PROTECT command to unlock the device first to prevent accidental/spurious writes.

  • The external EEPROM needs to be enabled by setting the EXT_EEPROM bit in the DEVICE_CONFIG register. In addition, it is done by configuring two (2) of the four (4) GPIOs as EECLK and EEDATA appropriately in the GPIO_CONFIG_12 and GPIO_CONFIG_34 registers. Make sure those two (2) selected GPIO pins are physically connected to the EEPROM clock and data pins respectively on the board.

  • The MEMORY_FLT bit in the STATUS_CML register gets set if the STORE_USER_ALL command is unsuccessful. TI recommends reading the STATUS_CML register after sending the STORE_USER_ALL command to verify whether it was successful or not.

  • The NVM inside the TPS25990x eFuse only has two (2) one-time programmable banks available for user programming. If an external EEPROM is not used, before sending the STORE_USER_ALL command the user should ensure that at least one bank of internal NVM is available for programming by reading the CONFIG_NVM_STAT bit in the STATUS_MFR_SPECIFIC_2 register.